VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

Emilliano, Chandan Kumar Chakrabarty, Ahmad Basri Abdul Ghani, Agileswari Ramasamy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in high voltage underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. The output signals of peak detector block, 64 bit BCD counter with reset block and reset automatic block is processed using reset automatic block and 64 bit latch block for keep output data in LCD to constant when the 64 bit BCD counter block is reset and return to zero again until update new data again. The combination of all blocks of PD detection circuit system is tested by using ISE simulator. In the next stage, this method will be implemented on a lab simulation scale for testing and validation.

Original languageEnglish
Title of host publicationProceedings - ICSGRC 2010
Subtitle of host publication2010 IEEE Control and System Graduate Research Colloquium
Pages14-19
Number of pages6
DOIs
Publication statusPublished - 2010
Event2010 IEEE Control and System Graduate Research Colloquium, ICSGRC 2010 - Shah Alam, Malaysia
Duration: 22 Jun 201022 Jun 2010

Other

Other2010 IEEE Control and System Graduate Research Colloquium, ICSGRC 2010
CountryMalaysia
CityShah Alam
Period22/06/1022/06/10

Fingerprint

Computer hardware description languages
Partial discharges
Computer programming
Networks (circuits)
Simulators
Underground cables
Liquid crystal displays
Integrated circuits
Detectors
Testing
Electric potential

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering

Cite this

Emilliano, Kumar Chakrabarty, C., Ghani, A. B. A., & Ramasamy, A. (2010). VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA. In Proceedings - ICSGRC 2010: 2010 IEEE Control and System Graduate Research Colloquium (pp. 14-19). [5562530] https://doi.org/10.1109/ICSGRC.2010.5562530
Emilliano, ; Kumar Chakrabarty, Chandan ; Ghani, Ahmad Basri Abdul ; Ramasamy, Agileswari. / VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA. Proceedings - ICSGRC 2010: 2010 IEEE Control and System Graduate Research Colloquium. 2010. pp. 14-19
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Emilliano, , Kumar Chakrabarty, C, Ghani, ABA & Ramasamy, A 2010, VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA. in Proceedings - ICSGRC 2010: 2010 IEEE Control and System Graduate Research Colloquium., 5562530, pp. 14-19, 2010 IEEE Control and System Graduate Research Colloquium, ICSGRC 2010, Shah Alam, Malaysia, 22/06/10. https://doi.org/10.1109/ICSGRC.2010.5562530

VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA. / Emilliano, ; Kumar Chakrabarty, Chandan; Ghani, Ahmad Basri Abdul; Ramasamy, Agileswari.

Proceedings - ICSGRC 2010: 2010 IEEE Control and System Graduate Research Colloquium. 2010. p. 14-19 5562530.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Emilliano , Kumar Chakrabarty C, Ghani ABA, Ramasamy A. VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA. In Proceedings - ICSGRC 2010: 2010 IEEE Control and System Graduate Research Colloquium. 2010. p. 14-19. 5562530 https://doi.org/10.1109/ICSGRC.2010.5562530