VHDL implementation of capacitor voltage balancing control with level-shifted PWM for modular multilevel converter

Chuen Ling Toh, Lars Einar Norum

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Power electronics converters are a key component in high voltage direct current (HVDC) power transmission. The modular multilevel converter (MMC) is one of the latest topologies to be proposed for this application. An MMC generates multilevel output voltage waveforms which reduces the harmonics contents significantly. This paper presents a VHDL implementation of the capacitor voltage balancing control and level-shifted pulse width modulation (LSPWM) for MMC. The objective is to minimize the processing time with minimum gate counts. The design details are fully described and validated experimentally. An experiment is conducted on a small scale MMC prototype with two units of power cells on each arm. The test results are enclosed and discussed.

Original languageEnglish
Pages (from-to)94-106
Number of pages13
JournalInternational Journal of Power Electronics and Drive Systems
Volume7
Issue number1
DOIs
Publication statusPublished - Mar 2016

Fingerprint

Computer hardware description languages
Pulse width modulation
Capacitors
Electric potential
DC power transmission
Power electronics
Topology
Processing
Experiments

All Science Journal Classification (ASJC) codes

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering

Cite this

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