Threshold voltage optimization in a 22nm High-k/Salicide PMOS device

A. H. Afifah Maheran, P. S. Menon, Ibrahim Ahmad, Z. Yusoff

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this article, we examine the effect of four process parameters and two noise parameters on the threshold voltage (Vth) of a 22nm gate length PMOS device. The gate of the device uses titanium dioxide (TiO2) as the high permittivity material (high-k) layer to replace the traditional silicon dioxide (SiO2) dielectric layer. While the polysilicon (poly-Si) which is also known as self-aligned silicide (SALICIDE) layer, is deposited on top of the high-k dielectric layer and is used to reduce the gate electrode resistance. The virtual fabrication device was designed using the ATHENA and electrical characterization was simulated using ATLAS. These two simulators were combined with the L9 Taguchi's experimental design to aid in the design and optimization of the process parameters for a total of 36 simulation runs. The objective is to minimize the variance in Vth using Taguchi's nominal-the-best signal-to-noise ratio (SNR) analysis. Analysis of the mean (ANOM) was used to determine the best settings for the process parameters while Analysis of variance (ANOVA) was used to reduce the variability of V th. The results show that the Vth values with the least variance is -0.289 V ± 12.7% which is well within the prediction by the International Technology Roadmap for Semiconductors (ITRS) 2011.

Original languageEnglish
Title of host publicationProceedings - RSM 2013
Subtitle of host publication2013 IEEE Regional Symposium on Micro and Nano Electronics
Pages126-129
Number of pages4
DOIs
Publication statusPublished - 01 Dec 2013
Event2013 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2013 - Langkawi, Malaysia
Duration: 25 Sep 201327 Sep 2013

Other

Other2013 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2013
CountryMalaysia
CityLangkawi
Period25/09/1327/09/13

Fingerprint

Analysis of variance (ANOVA)
Threshold voltage
Polysilicon
Design of experiments
Titanium dioxide
Signal to noise ratio
Permittivity
Simulators
Silica
Semiconductor materials
Fabrication
Electrodes
High-k dielectric

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Afifah Maheran, A. H., Menon, P. S., Ahmad, I., & Yusoff, Z. (2013). Threshold voltage optimization in a 22nm High-k/Salicide PMOS device. In Proceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics (pp. 126-129). [6706489] https://doi.org/10.1109/RSM.2013.6706489
Afifah Maheran, A. H. ; Menon, P. S. ; Ahmad, Ibrahim ; Yusoff, Z. / Threshold voltage optimization in a 22nm High-k/Salicide PMOS device. Proceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics. 2013. pp. 126-129
@inproceedings{afc149020320486a967d85afc9c05b0b,
title = "Threshold voltage optimization in a 22nm High-k/Salicide PMOS device",
abstract = "In this article, we examine the effect of four process parameters and two noise parameters on the threshold voltage (Vth) of a 22nm gate length PMOS device. The gate of the device uses titanium dioxide (TiO2) as the high permittivity material (high-k) layer to replace the traditional silicon dioxide (SiO2) dielectric layer. While the polysilicon (poly-Si) which is also known as self-aligned silicide (SALICIDE) layer, is deposited on top of the high-k dielectric layer and is used to reduce the gate electrode resistance. The virtual fabrication device was designed using the ATHENA and electrical characterization was simulated using ATLAS. These two simulators were combined with the L9 Taguchi's experimental design to aid in the design and optimization of the process parameters for a total of 36 simulation runs. The objective is to minimize the variance in Vth using Taguchi's nominal-the-best signal-to-noise ratio (SNR) analysis. Analysis of the mean (ANOM) was used to determine the best settings for the process parameters while Analysis of variance (ANOVA) was used to reduce the variability of V th. The results show that the Vth values with the least variance is -0.289 V ± 12.7{\%} which is well within the prediction by the International Technology Roadmap for Semiconductors (ITRS) 2011.",
author = "{Afifah Maheran}, {A. H.} and Menon, {P. S.} and Ibrahim Ahmad and Z. Yusoff",
year = "2013",
month = "12",
day = "1",
doi = "10.1109/RSM.2013.6706489",
language = "English",
isbn = "9781479911837",
pages = "126--129",
booktitle = "Proceedings - RSM 2013",

}

Afifah Maheran, AH, Menon, PS, Ahmad, I & Yusoff, Z 2013, Threshold voltage optimization in a 22nm High-k/Salicide PMOS device. in Proceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics., 6706489, pp. 126-129, 2013 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2013, Langkawi, Malaysia, 25/09/13. https://doi.org/10.1109/RSM.2013.6706489

Threshold voltage optimization in a 22nm High-k/Salicide PMOS device. / Afifah Maheran, A. H.; Menon, P. S.; Ahmad, Ibrahim; Yusoff, Z.

Proceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics. 2013. p. 126-129 6706489.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Threshold voltage optimization in a 22nm High-k/Salicide PMOS device

AU - Afifah Maheran, A. H.

AU - Menon, P. S.

AU - Ahmad, Ibrahim

AU - Yusoff, Z.

PY - 2013/12/1

Y1 - 2013/12/1

N2 - In this article, we examine the effect of four process parameters and two noise parameters on the threshold voltage (Vth) of a 22nm gate length PMOS device. The gate of the device uses titanium dioxide (TiO2) as the high permittivity material (high-k) layer to replace the traditional silicon dioxide (SiO2) dielectric layer. While the polysilicon (poly-Si) which is also known as self-aligned silicide (SALICIDE) layer, is deposited on top of the high-k dielectric layer and is used to reduce the gate electrode resistance. The virtual fabrication device was designed using the ATHENA and electrical characterization was simulated using ATLAS. These two simulators were combined with the L9 Taguchi's experimental design to aid in the design and optimization of the process parameters for a total of 36 simulation runs. The objective is to minimize the variance in Vth using Taguchi's nominal-the-best signal-to-noise ratio (SNR) analysis. Analysis of the mean (ANOM) was used to determine the best settings for the process parameters while Analysis of variance (ANOVA) was used to reduce the variability of V th. The results show that the Vth values with the least variance is -0.289 V ± 12.7% which is well within the prediction by the International Technology Roadmap for Semiconductors (ITRS) 2011.

AB - In this article, we examine the effect of four process parameters and two noise parameters on the threshold voltage (Vth) of a 22nm gate length PMOS device. The gate of the device uses titanium dioxide (TiO2) as the high permittivity material (high-k) layer to replace the traditional silicon dioxide (SiO2) dielectric layer. While the polysilicon (poly-Si) which is also known as self-aligned silicide (SALICIDE) layer, is deposited on top of the high-k dielectric layer and is used to reduce the gate electrode resistance. The virtual fabrication device was designed using the ATHENA and electrical characterization was simulated using ATLAS. These two simulators were combined with the L9 Taguchi's experimental design to aid in the design and optimization of the process parameters for a total of 36 simulation runs. The objective is to minimize the variance in Vth using Taguchi's nominal-the-best signal-to-noise ratio (SNR) analysis. Analysis of the mean (ANOM) was used to determine the best settings for the process parameters while Analysis of variance (ANOVA) was used to reduce the variability of V th. The results show that the Vth values with the least variance is -0.289 V ± 12.7% which is well within the prediction by the International Technology Roadmap for Semiconductors (ITRS) 2011.

UR - http://www.scopus.com/inward/record.url?scp=84893619716&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84893619716&partnerID=8YFLogxK

U2 - 10.1109/RSM.2013.6706489

DO - 10.1109/RSM.2013.6706489

M3 - Conference contribution

SN - 9781479911837

SP - 126

EP - 129

BT - Proceedings - RSM 2013

ER -

Afifah Maheran AH, Menon PS, Ahmad I, Yusoff Z. Threshold voltage optimization in a 22nm High-k/Salicide PMOS device. In Proceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics. 2013. p. 126-129. 6706489 https://doi.org/10.1109/RSM.2013.6706489