Threshold voltage and leakage current variability on process parameter in a 22nm PMOS Device

A. H. Afifah Maheran, P. S. Menon, Ibrahim Ahmad, Z. A. Noor Faizah, A. S. Mohd Zain, F. Salehuddin, Nuraini M. Sayed

Research output: Contribution to journalArticle

Abstract

This article explains the effect of variation on the process parameters while designing a Nano-scaled planar PMOS device in complementary metal-oxide-semiconductor (CMOS) technology for 22 nm gate length. This procedure aims to meet the best combination of fabrication process parameter on the threshold voltage (VTH) and leakage current (IOFF) which was predicted by the International Technology Roadmap for Semiconductors (ITRS). The gate structure of the PMOS device consists of Titanium Dioxide (TiO2) as the high permittivity material (high-k) dielectric and Tungsten Silicide (WSix) metal gate where it is deposited on top of the TiO2 high-k layer. The simulation process was designed using an industrial-based numerical simulator. This simulator was then aided in design with the L9 Taguchi’s orthogonal array method to optimise the best combination of process parameters in order to achieve the optimum VTH value with the lowest IOFF. The analysis results of the factor effect on the SNR in ANOVA analysis clearly show that the Halo implantation tilting angle has the greatest influence with 52.47% in optimising the process parameter where the implantation tilting angle is at 35°. The final results in characterizing and modelling the process parameters of the 22 nm PMOS device with reference to the prediction ITRS succeeded where the result of the VTH is 4.25% closest to the prediction value of -0.289 V ± 12.7% and minimum IOFF value which is 92% away from the predicted value which is 100 nA/µm.

Original languageEnglish
Pages (from-to)9-13
Number of pages5
JournalJournal of Telecommunication, Electronic and Computer Engineering
Volume10
Issue number2-8
Publication statusPublished - 01 Jan 2018

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Threshold voltage
Leakage currents
Simulators
Semiconductor materials
Analysis of variance (ANOVA)
Metals
Titanium dioxide
Tungsten
Permittivity
Fabrication

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Afifah Maheran, A. H., Menon, P. S., Ahmad, I., Noor Faizah, Z. A., Mohd Zain, A. S., Salehuddin, F., & Sayed, N. M. (2018). Threshold voltage and leakage current variability on process parameter in a 22nm PMOS Device. Journal of Telecommunication, Electronic and Computer Engineering, 10(2-8), 9-13.
Afifah Maheran, A. H. ; Menon, P. S. ; Ahmad, Ibrahim ; Noor Faizah, Z. A. ; Mohd Zain, A. S. ; Salehuddin, F. ; Sayed, Nuraini M. / Threshold voltage and leakage current variability on process parameter in a 22nm PMOS Device. In: Journal of Telecommunication, Electronic and Computer Engineering. 2018 ; Vol. 10, No. 2-8. pp. 9-13.
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abstract = "This article explains the effect of variation on the process parameters while designing a Nano-scaled planar PMOS device in complementary metal-oxide-semiconductor (CMOS) technology for 22 nm gate length. This procedure aims to meet the best combination of fabrication process parameter on the threshold voltage (VTH) and leakage current (IOFF) which was predicted by the International Technology Roadmap for Semiconductors (ITRS). The gate structure of the PMOS device consists of Titanium Dioxide (TiO2) as the high permittivity material (high-k) dielectric and Tungsten Silicide (WSix) metal gate where it is deposited on top of the TiO2 high-k layer. The simulation process was designed using an industrial-based numerical simulator. This simulator was then aided in design with the L9 Taguchi’s orthogonal array method to optimise the best combination of process parameters in order to achieve the optimum VTH value with the lowest IOFF. The analysis results of the factor effect on the SNR in ANOVA analysis clearly show that the Halo implantation tilting angle has the greatest influence with 52.47{\%} in optimising the process parameter where the implantation tilting angle is at 35°. The final results in characterizing and modelling the process parameters of the 22 nm PMOS device with reference to the prediction ITRS succeeded where the result of the VTH is 4.25{\%} closest to the prediction value of -0.289 V ± 12.7{\%} and minimum IOFF value which is 92{\%} away from the predicted value which is 100 nA/µm.",
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Afifah Maheran, AH, Menon, PS, Ahmad, I, Noor Faizah, ZA, Mohd Zain, AS, Salehuddin, F & Sayed, NM 2018, 'Threshold voltage and leakage current variability on process parameter in a 22nm PMOS Device', Journal of Telecommunication, Electronic and Computer Engineering, vol. 10, no. 2-8, pp. 9-13.

Threshold voltage and leakage current variability on process parameter in a 22nm PMOS Device. / Afifah Maheran, A. H.; Menon, P. S.; Ahmad, Ibrahim; Noor Faizah, Z. A.; Mohd Zain, A. S.; Salehuddin, F.; Sayed, Nuraini M.

In: Journal of Telecommunication, Electronic and Computer Engineering, Vol. 10, No. 2-8, 01.01.2018, p. 9-13.

Research output: Contribution to journalArticle

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AU - Afifah Maheran, A. H.

AU - Menon, P. S.

AU - Ahmad, Ibrahim

AU - Noor Faizah, Z. A.

AU - Mohd Zain, A. S.

AU - Salehuddin, F.

AU - Sayed, Nuraini M.

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