This article explains the effect of variation on the process parameters while designing a Nano-scaled planar PMOS device in complementary metal-oxide-semiconductor (CMOS) technology for 22 nm gate length. This procedure aims to meet the best combination of fabrication process parameter on the threshold voltage (VTH) and leakage current (IOFF) which was predicted by the International Technology Roadmap for Semiconductors (ITRS). The gate structure of the PMOS device consists of Titanium Dioxide (TiO2) as the high permittivity material (high-k) dielectric and Tungsten Silicide (WSix) metal gate where it is deposited on top of the TiO2 high-k layer. The simulation process was designed using an industrial-based numerical simulator. This simulator was then aided in design with the L9 Taguchi’s orthogonal array method to optimise the best combination of process parameters in order to achieve the optimum VTH value with the lowest IOFF. The analysis results of the factor effect on the SNR in ANOVA analysis clearly show that the Halo implantation tilting angle has the greatest influence with 52.47% in optimising the process parameter where the implantation tilting angle is at 35°. The final results in characterizing and modelling the process parameters of the 22 nm PMOS device with reference to the prediction ITRS succeeded where the result of the VTH is 4.25% closest to the prediction value of -0.289 V ± 12.7% and minimum IOFF value which is 92% away from the predicted value which is 100 nA/µm.
|Number of pages||5|
|Journal||Journal of Telecommunication, Electronic and Computer Engineering|
|Publication status||Published - 01 Jan 2018|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Networks and Communications
- Electrical and Electronic Engineering