TCAD simulation of local mechanical stress reduction by use of a compressive silicon nitride/silicon oxynitride etch stop bi-layer for CMOS performance enhancement

Wan Rosmaria Wan Ahmad, Albert Victor Kordesch, Ibrahim Ahmad, Soon Aik Chew, Philip Tan Beow Yew

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we investigate the mechanism of local mechanical stress reduction in CMOS transistors by improving the Inter Layer Dielectric (ILD) process. We changed the Etch Stop Liner (ESL) from single stack silicon nitride (SiN) to dual stack ESL SiN/SiON similar to [1]. We then simulate the stress in 2-D for both n- and p- channel MOSFET, and investigate how an oxynitride (SiON) buffer layer under the SiN ESL can reduce the longitudinal (X) and the lateral (Y) stress in both n- and p- channel thus improving the overall CMOS performance. Our result shows that the dual SiN/SiON layer reduces the stress in the channel length direction (Sxx), perpendicular to channel plane direction (Syy) and channel width direction (Szz). It is known that decreasing the compressive stress in the X direction improves NMOS but degrades PMOS. Our experimental data shows that the additional SiON layer reduces the stress in the channel, hence increases the electron mobility.

Original languageEnglish
Title of host publicationProceedings of the IEMT 2006 31st International Conference on Electronics Manufacturing and Technology
Pages411-415
Number of pages5
DOIs
Publication statusPublished - 2006
Event31st International Electronics Manufacturing Technology Conference, IEMT 2006 - Petaling Jaya, Malaysia
Duration: 08 Nov 200610 Nov 2006

Other

Other31st International Electronics Manufacturing Technology Conference, IEMT 2006
CountryMalaysia
CityPetaling Jaya
Period08/11/0610/11/06

Fingerprint

Silicon nitride
Silicon
Electron mobility
Buffer layers
Compressive stress
Transistors

All Science Journal Classification (ASJC) codes

  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

Cite this

Ahmad, W. R. W., Kordesch, A. V., Ahmad, I., Chew, S. A., & Yew, P. T. B. (2006). TCAD simulation of local mechanical stress reduction by use of a compressive silicon nitride/silicon oxynitride etch stop bi-layer for CMOS performance enhancement. In Proceedings of the IEMT 2006 31st International Conference on Electronics Manufacturing and Technology (pp. 411-415). [4456487] https://doi.org/10.1109/IEMT.2006.4456487
Ahmad, Wan Rosmaria Wan ; Kordesch, Albert Victor ; Ahmad, Ibrahim ; Chew, Soon Aik ; Yew, Philip Tan Beow. / TCAD simulation of local mechanical stress reduction by use of a compressive silicon nitride/silicon oxynitride etch stop bi-layer for CMOS performance enhancement. Proceedings of the IEMT 2006 31st International Conference on Electronics Manufacturing and Technology. 2006. pp. 411-415
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Ahmad, WRW, Kordesch, AV, Ahmad, I, Chew, SA & Yew, PTB 2006, TCAD simulation of local mechanical stress reduction by use of a compressive silicon nitride/silicon oxynitride etch stop bi-layer for CMOS performance enhancement. in Proceedings of the IEMT 2006 31st International Conference on Electronics Manufacturing and Technology., 4456487, pp. 411-415, 31st International Electronics Manufacturing Technology Conference, IEMT 2006, Petaling Jaya, Malaysia, 08/11/06. https://doi.org/10.1109/IEMT.2006.4456487

TCAD simulation of local mechanical stress reduction by use of a compressive silicon nitride/silicon oxynitride etch stop bi-layer for CMOS performance enhancement. / Ahmad, Wan Rosmaria Wan; Kordesch, Albert Victor; Ahmad, Ibrahim; Chew, Soon Aik; Yew, Philip Tan Beow.

Proceedings of the IEMT 2006 31st International Conference on Electronics Manufacturing and Technology. 2006. p. 411-415 4456487.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Ahmad WRW, Kordesch AV, Ahmad I, Chew SA, Yew PTB. TCAD simulation of local mechanical stress reduction by use of a compressive silicon nitride/silicon oxynitride etch stop bi-layer for CMOS performance enhancement. In Proceedings of the IEMT 2006 31st International Conference on Electronics Manufacturing and Technology. 2006. p. 411-415. 4456487 https://doi.org/10.1109/IEMT.2006.4456487