Statistical process modelling for 32nm high-K/metal gate PMOS device

A. H.Afifah Maheran, Z. A. Noor Faizah, P. S. Menon, Ibrahim Ahmad, P. R. Apte, T. Kalaivani, F. Salehuddin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (VTH) and leakage current (IOFF). The simulation result shows that the optimal value of VTH and IOFF which are 0.1030075V and 3.4264075×10-12A/um respectively are well within ITRS prediction.

Original languageEnglish
Title of host publicationIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages232-235
Number of pages4
ISBN (Electronic)9781479957606
DOIs
Publication statusPublished - 10 Oct 2014
Event11th IEEE International Conference on Semiconductor Electronics, ICSE 2014 - Kuala Lumpur, Malaysia
Duration: 27 Aug 201429 Aug 2014

Publication series

NameIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE

Other

Other11th IEEE International Conference on Semiconductor Electronics, ICSE 2014
CountryMalaysia
CityKuala Lumpur
Period27/08/1429/08/14

Fingerprint

Metals
Fabrication
Transistors
Silicon
Threshold voltage
Leakage currents
Experiments
thiazole-4-carboxamide adenine dinucleotide

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Maheran, A. H. A., Noor Faizah, Z. A., Menon, P. S., Ahmad, I., Apte, P. R., Kalaivani, T., & Salehuddin, F. (2014). Statistical process modelling for 32nm high-K/metal gate PMOS device. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE (pp. 232-235). [6920839] (IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SMELEC.2014.6920839
Maheran, A. H.Afifah ; Noor Faizah, Z. A. ; Menon, P. S. ; Ahmad, Ibrahim ; Apte, P. R. ; Kalaivani, T. ; Salehuddin, F. / Statistical process modelling for 32nm high-K/metal gate PMOS device. IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 232-235 (IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE).
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abstract = "The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (VTH) and leakage current (IOFF). The simulation result shows that the optimal value of VTH and IOFF which are 0.1030075V and 3.4264075×10-12A/um respectively are well within ITRS prediction.",
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Maheran, AHA, Noor Faizah, ZA, Menon, PS, Ahmad, I, Apte, PR, Kalaivani, T & Salehuddin, F 2014, Statistical process modelling for 32nm high-K/metal gate PMOS device. in IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE., 6920839, IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE, Institute of Electrical and Electronics Engineers Inc., pp. 232-235, 11th IEEE International Conference on Semiconductor Electronics, ICSE 2014, Kuala Lumpur, Malaysia, 27/08/14. https://doi.org/10.1109/SMELEC.2014.6920839

Statistical process modelling for 32nm high-K/metal gate PMOS device. / Maheran, A. H.Afifah; Noor Faizah, Z. A.; Menon, P. S.; Ahmad, Ibrahim; Apte, P. R.; Kalaivani, T.; Salehuddin, F.

IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. Institute of Electrical and Electronics Engineers Inc., 2014. p. 232-235 6920839 (IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (VTH) and leakage current (IOFF). The simulation result shows that the optimal value of VTH and IOFF which are 0.1030075V and 3.4264075×10-12A/um respectively are well within ITRS prediction.

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Maheran AHA, Noor Faizah ZA, Menon PS, Ahmad I, Apte PR, Kalaivani T et al. Statistical process modelling for 32nm high-K/metal gate PMOS device. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. Institute of Electrical and Electronics Engineers Inc. 2014. p. 232-235. 6920839. (IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE). https://doi.org/10.1109/SMELEC.2014.6920839