This paper focuses on virtual modelling and optimization of 14nm n-types planar MOSFET. Here, high-k dielectric and metal gate were used where the high-k material is Hafnium Dioxide (HfO2) and the metal gate is Tungsten Silicide (WSi2). 36 simulations of Taguchi L9 Orthogonal Array method were applied in order to obtain the best parameter design for optimization of both performance parameters which are threshold voltage (VTH) and leakage current (IOFF). The simulation and fabrication for n-type transistor was conducted through Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools named ATHENA and ATLAS for its electrical characterization. For analyzation of the impact parameters on VTH and IOFF, two noise parameters and four process parameters value were varied. From the simulations, the results show the best value were well within ITRS prediction where VTH and IOFF are 0.236737 V and 6.995705 nA/um respectively.
|Number of pages||5|
|Journal||Journal of Telecommunication, Electronic and Computer Engineering|
|Publication status||Published - 01 Jan 2016|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Computer Networks and Communications
- Electrical and Electronic Engineering