Solder bump strength and failure mode of low-k flip chip device

Zulkarnain Endut, Ibrahim Ahmad, Gary Lee How Swee, Norazham Mohd Sukemi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, the failure mode and solder bump strength for low-k flip chip devices were determined using die pull technique. The results show there is no significant difference between low-k and non low-k devices in terms of bumps strength for the amount of taffy in this device. However, there is different in failure mode which shows an increasing in VRO and SRO failure mode. Die pull test within a time and bake factor also help to minimize VRO and SRO failure mode. However, VRO and SRO failure mode were expected as an another impact of low-k materials on flip chip packaging.

Original languageEnglish
Title of host publicationICSE 2006
Subtitle of host publication2006 IEEE International Conference on Semiconductor Electronics, Proceedings
Pages991-995
Number of pages5
DOIs
Publication statusPublished - 01 Dec 2006
Event2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006 - Kuala Lumpur, Malaysia
Duration: 29 Nov 200601 Dec 2006

Publication series

NameIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE

Other

Other2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006
CountryMalaysia
CityKuala Lumpur
Period29/11/0601/12/06

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Endut, Z., Ahmad, I., Swee, G. L. H., & Sukemi, N. M. (2006). Solder bump strength and failure mode of low-k flip chip device. In ICSE 2006: 2006 IEEE International Conference on Semiconductor Electronics, Proceedings (pp. 991-995). [4266770] (IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE). https://doi.org/10.1109/SMELEC.2006.380787