Simulation of fabrication process VDMOSFET transistor using Silvaco software

H. Abdullah, J. Jurait, A. Lennie, Z. M. Nopiah, Ibrahim Ahmad

Research output: Contribution to journalArticle

23 Citations (Scopus)

Abstract

Taguchi Method is being applied in to find the sequence of dominance for factors that determine the performance of a VDMOSFET power transistor. The main objective of this project is to optimize the trench depth, trench width, epitaxial resistivity and thickness in power VDMOSFET so as to obtain high breakdown voltage but low on-resistance. Optimization of trench depth, trench width, epitaxial resistivity and epitaxial thickness are based on L9 array. Taguchi Method was being applied to reduce development time and to ensure that the products are in the acceptable quality range. The robust nature of Taguchi Method pointed out the most dominant factors that will determine the performance and characteristics of the power transistor. ATHENA and ATLAS module of SILVACO software are the tools used in simulating the fabrication and also simulating the electrical performance of the transistors. The parameters under investigation were the threshold voltage (VTH), breakdown voltage (BV) and on-resistance (RON). The data produced from the experiments were used to determine the sequence of dominance for the factors involved in the transistor's characteristics. Taguchi suggests that to analyzing Signal-to-Noise ratios (S/N) by using conceptual approach that involves graphing the effects and visually identifying the factors that show to be significant. The slopes of the lines also show the relative influence of the factor to the variability of results. The Pareto ANOVA method is used to analyze the data for process optimization. This is a quick and easy method for analyzing results of parameter design that does not require an ANOVA table and does not use F-tests. This method enables the significance of factors to be evaluated by Pareto type analysis. It also allows the optimal levels of factors to be obtained. From the experimental results, the trench depth, epitaxial resistance, and epitaxial are significant factors toward breakdown voltage and on-resistance in n-channel VDMOSFET.

Original languageEnglish
Pages (from-to)461-470
Number of pages10
JournalEuropean Journal of Scientific Research
Volume29
Issue number4
Publication statusPublished - 01 Jan 2009

Fingerprint

Taguchi methods
Electric breakdown
Fabrication
Transistors
Software
trench
Analysis of variance (ANOVA)
software
analysis of variance
Taguchi Method
simulation
Simulation
Breakdown
Threshold voltage
electrical resistivity
Voltage
Signal to noise ratio
Analysis of Variance
Resistivity
methodology

All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Mathematics(all)
  • Materials Science(all)
  • Agricultural and Biological Sciences(all)
  • Engineering(all)
  • Earth and Planetary Sciences(all)

Cite this

Abdullah, H. ; Jurait, J. ; Lennie, A. ; Nopiah, Z. M. ; Ahmad, Ibrahim. / Simulation of fabrication process VDMOSFET transistor using Silvaco software. In: European Journal of Scientific Research. 2009 ; Vol. 29, No. 4. pp. 461-470.
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Abdullah, H, Jurait, J, Lennie, A, Nopiah, ZM & Ahmad, I 2009, 'Simulation of fabrication process VDMOSFET transistor using Silvaco software', European Journal of Scientific Research, vol. 29, no. 4, pp. 461-470.

Simulation of fabrication process VDMOSFET transistor using Silvaco software. / Abdullah, H.; Jurait, J.; Lennie, A.; Nopiah, Z. M.; Ahmad, Ibrahim.

In: European Journal of Scientific Research, Vol. 29, No. 4, 01.01.2009, p. 461-470.

Research output: Contribution to journalArticle

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