Abstract
In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work.
| Original language | English |
|---|---|
| Title of host publication | 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings |
| Pages | 173-176 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2012 |
| Event | 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Kuala Lumpur, Malaysia Duration: 19 Sep 2012 → 21 Sep 2012 |
Other
| Other | 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 |
|---|---|
| Country | Malaysia |
| City | Kuala Lumpur |
| Period | 19/09/12 → 21/09/12 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
}
Scaling down of the 32 nm to 22 nm gate length NMOS transistor. / Afifah Maheran, A. H.; Menon, P. S.; Ahmad, Ibrahim; Elgomati, H. A.; Majlis, B. Y.; Salehuddin, F.
2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings. 2012. p. 173-176 6417117.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Scaling down of the 32 nm to 22 nm gate length NMOS transistor
AU - Afifah Maheran, A. H.
AU - Menon, P. S.
AU - Ahmad, Ibrahim
AU - Elgomati, H. A.
AU - Majlis, B. Y.
AU - Salehuddin, F.
PY - 2012
Y1 - 2012
N2 - In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work.
AB - In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work.
UR - http://www.scopus.com/inward/record.url?scp=84874126874&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84874126874&partnerID=8YFLogxK
U2 - 10.1109/SMElec.2012.6417117
DO - 10.1109/SMElec.2012.6417117
M3 - Conference contribution
AN - SCOPUS:84874126874
SN - 9781467323963
SP - 173
EP - 176
BT - 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings
ER -