Scaling down of the 32 nm to 22 nm gate length NMOS transistor

A. H. Afifah Maheran, P. S. Menon, Ibrahim Ahmad, H. A. Elgomati, B. Y. Majlis, F. Salehuddin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work.

Original languageEnglish
Title of host publication2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings
Pages173-176
Number of pages4
DOIs
Publication statusPublished - 2012
Event2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Kuala Lumpur, Malaysia
Duration: 19 Sep 2012 → 21 Sep 2012

Other

Other2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012
CountryMalaysia
CityKuala Lumpur
Period19/09/12 → 21/09/12

Fingerprint

Transistors
Fabrication
Threshold voltage
Leakage currents
Titanium dioxide
Tungsten
Specifications
Ions
Metals

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Afifah Maheran, A. H., Menon, P. S., Ahmad, I., Elgomati, H. A., Majlis, B. Y., & Salehuddin, F. (2012). Scaling down of the 32 nm to 22 nm gate length NMOS transistor. In 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings (pp. 173-176). [6417117] https://doi.org/10.1109/SMElec.2012.6417117
Afifah Maheran, A. H. ; Menon, P. S. ; Ahmad, Ibrahim ; Elgomati, H. A. ; Majlis, B. Y. ; Salehuddin, F. / Scaling down of the 32 nm to 22 nm gate length NMOS transistor. 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings. 2012. pp. 173-176
@inproceedings{db78e289dcbd4e12b2a763de8f228335,
title = "Scaling down of the 32 nm to 22 nm gate length NMOS transistor",
abstract = "In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work.",
author = "{Afifah Maheran}, {A. H.} and Menon, {P. S.} and Ibrahim Ahmad and Elgomati, {H. A.} and Majlis, {B. Y.} and F. Salehuddin",
year = "2012",
doi = "10.1109/SMElec.2012.6417117",
language = "English",
isbn = "9781467323963",
pages = "173--176",
booktitle = "2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings",

}

Afifah Maheran, AH, Menon, PS, Ahmad, I, Elgomati, HA, Majlis, BY & Salehuddin, F 2012, Scaling down of the 32 nm to 22 nm gate length NMOS transistor. in 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings., 6417117, pp. 173-176, 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012, Kuala Lumpur, Malaysia, 19/09/12. https://doi.org/10.1109/SMElec.2012.6417117

Scaling down of the 32 nm to 22 nm gate length NMOS transistor. / Afifah Maheran, A. H.; Menon, P. S.; Ahmad, Ibrahim; Elgomati, H. A.; Majlis, B. Y.; Salehuddin, F.

2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings. 2012. p. 173-176 6417117.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Scaling down of the 32 nm to 22 nm gate length NMOS transistor

AU - Afifah Maheran, A. H.

AU - Menon, P. S.

AU - Ahmad, Ibrahim

AU - Elgomati, H. A.

AU - Majlis, B. Y.

AU - Salehuddin, F.

PY - 2012

Y1 - 2012

N2 - In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work.

AB - In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work.

UR - http://www.scopus.com/inward/record.url?scp=84874126874&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84874126874&partnerID=8YFLogxK

U2 - 10.1109/SMElec.2012.6417117

DO - 10.1109/SMElec.2012.6417117

M3 - Conference contribution

SN - 9781467323963

SP - 173

EP - 176

BT - 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings

ER -

Afifah Maheran AH, Menon PS, Ahmad I, Elgomati HA, Majlis BY, Salehuddin F. Scaling down of the 32 nm to 22 nm gate length NMOS transistor. In 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings. 2012. p. 173-176. 6417117 https://doi.org/10.1109/SMElec.2012.6417117

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