RF substrate noise characterization for CMOS 0.18μm

Izahan Syemylona Ishak, Richard Alan Keating, Chandan Kumar Chakrabarty

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

In the submicron technologies, RF noise isolation is becoming increasingly important. In this paper, the investigations of the on-chip RF isolation techniques were carried out. The chosen isolation structures were the Deep Nwell (or triple well isolation) and the P+ Guard Ring. The test structures were designed and fabricated using Silterra CMOS 0.18μm Mixed Signal process. The design parameter investigated was the distance between the isolation ring and the output terminal (Sout) in which the substrate coupling effects with and without deep nwell were characterized.

Original languageEnglish
Title of host publication2004 RF and Microwave Conference, RFM 2004 - Proceedings
EditorsD.K. Ghodgaonkar, M. Esa, A. Lin, Z. Awang, R.W. Habash
Pages60-63
Number of pages4
Publication statusPublished - 2004
Event2004 RF and Microwave Conference, RFM 2004 - Selangor, Malaysia
Duration: 05 Oct 200406 Oct 2004

Other

Other2004 RF and Microwave Conference, RFM 2004
CountryMalaysia
CitySelangor
Period05/10/0406/10/04

Fingerprint

Substrates

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Ishak, I. S., Keating, R. A., & Kumar Chakrabarty, C. (2004). RF substrate noise characterization for CMOS 0.18μm. In D. K. Ghodgaonkar, M. Esa, A. Lin, Z. Awang, & R. W. Habash (Eds.), 2004 RF and Microwave Conference, RFM 2004 - Proceedings (pp. 60-63)
Ishak, Izahan Syemylona ; Keating, Richard Alan ; Kumar Chakrabarty, Chandan. / RF substrate noise characterization for CMOS 0.18μm. 2004 RF and Microwave Conference, RFM 2004 - Proceedings. editor / D.K. Ghodgaonkar ; M. Esa ; A. Lin ; Z. Awang ; R.W. Habash. 2004. pp. 60-63
@inproceedings{006567d3bf3a45b5b31da033908a0fa2,
title = "RF substrate noise characterization for CMOS 0.18μm",
abstract = "In the submicron technologies, RF noise isolation is becoming increasingly important. In this paper, the investigations of the on-chip RF isolation techniques were carried out. The chosen isolation structures were the Deep Nwell (or triple well isolation) and the P+ Guard Ring. The test structures were designed and fabricated using Silterra CMOS 0.18μm Mixed Signal process. The design parameter investigated was the distance between the isolation ring and the output terminal (Sout) in which the substrate coupling effects with and without deep nwell were characterized.",
author = "Ishak, {Izahan Syemylona} and Keating, {Richard Alan} and {Kumar Chakrabarty}, Chandan",
year = "2004",
language = "English",
isbn = "078038671X",
pages = "60--63",
editor = "D.K. Ghodgaonkar and M. Esa and A. Lin and Z. Awang and R.W. Habash",
booktitle = "2004 RF and Microwave Conference, RFM 2004 - Proceedings",

}

Ishak, IS, Keating, RA & Kumar Chakrabarty, C 2004, RF substrate noise characterization for CMOS 0.18μm. in DK Ghodgaonkar, M Esa, A Lin, Z Awang & RW Habash (eds), 2004 RF and Microwave Conference, RFM 2004 - Proceedings. pp. 60-63, 2004 RF and Microwave Conference, RFM 2004, Selangor, Malaysia, 05/10/04.

RF substrate noise characterization for CMOS 0.18μm. / Ishak, Izahan Syemylona; Keating, Richard Alan; Kumar Chakrabarty, Chandan.

2004 RF and Microwave Conference, RFM 2004 - Proceedings. ed. / D.K. Ghodgaonkar; M. Esa; A. Lin; Z. Awang; R.W. Habash. 2004. p. 60-63.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - RF substrate noise characterization for CMOS 0.18μm

AU - Ishak, Izahan Syemylona

AU - Keating, Richard Alan

AU - Kumar Chakrabarty, Chandan

PY - 2004

Y1 - 2004

N2 - In the submicron technologies, RF noise isolation is becoming increasingly important. In this paper, the investigations of the on-chip RF isolation techniques were carried out. The chosen isolation structures were the Deep Nwell (or triple well isolation) and the P+ Guard Ring. The test structures were designed and fabricated using Silterra CMOS 0.18μm Mixed Signal process. The design parameter investigated was the distance between the isolation ring and the output terminal (Sout) in which the substrate coupling effects with and without deep nwell were characterized.

AB - In the submicron technologies, RF noise isolation is becoming increasingly important. In this paper, the investigations of the on-chip RF isolation techniques were carried out. The chosen isolation structures were the Deep Nwell (or triple well isolation) and the P+ Guard Ring. The test structures were designed and fabricated using Silterra CMOS 0.18μm Mixed Signal process. The design parameter investigated was the distance between the isolation ring and the output terminal (Sout) in which the substrate coupling effects with and without deep nwell were characterized.

UR - http://www.scopus.com/inward/record.url?scp=29044444843&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=29044444843&partnerID=8YFLogxK

M3 - Conference contribution

SN - 078038671X

SN - 9780780386716

SP - 60

EP - 63

BT - 2004 RF and Microwave Conference, RFM 2004 - Proceedings

A2 - Ghodgaonkar, D.K.

A2 - Esa, M.

A2 - Lin, A.

A2 - Awang, Z.

A2 - Habash, R.W.

ER -

Ishak IS, Keating RA, Kumar Chakrabarty C. RF substrate noise characterization for CMOS 0.18μm. In Ghodgaonkar DK, Esa M, Lin A, Awang Z, Habash RW, editors, 2004 RF and Microwave Conference, RFM 2004 - Proceedings. 2004. p. 60-63