Reusable data-path architecture for encryption-then-authentication on FPGA

Yasir Amer Abbas, Razali Jidin, Norziana Jamil, Muhammad Reza Zaba

Research output: Contribution to journalArticle

Abstract

This paper proposes reusable data-path architecture for lightweight cryptography algorithms, reusing some similar hardware components for both encryption and authentication. In addition to efforts by many researches to optimize hardware architectures, to reduce hardware resources, our proposal is to reuse identical functional blocks within crypto-algorithms targeting for more secure cryptography like Message Authentication Code (MAC), authenticated encryption such as Encrypt-then-MAC (EtM) on Field Programmable Gate Arrays (FPGA). For this proposed reusable data-path, we have chosen LED algorithm for encryption and then PHOTON to generate the MAC code. Instead of creating two different circuits, one for PHOTON and another for LED, our proposal’s is to reuse some of identical block functions repeatedly, therefore reduce the size of required circuit area. Reuse of resources or identical functions however require controllers that enable sharing of data path that can also has different “rounds” of transforms required for different modes either PHOTON or LED in this case, in addition to controllers for individual algorithm. Also to enable comparable computation speed, the data-path has to be further refined, an improvement needed at least on par or better than the current techniques. For PHOTON data-path, we have improved performance of Mix-Columns, focusing on lengthy clock cycle of Galois polynomial multiplication. The results show that this proposed EtM hardware architecture achieves significant improvements, up to 587 MHz, 1336 Mbps and 3.2 Mbps/slices, for maximum frequency, throughput and efficiency, respectively.

Original languageEnglish
Pages (from-to)56-63
Number of pages8
JournalInternational Review on Computers and Software
Volume11
Issue number1
DOIs
Publication statusPublished - 01 Jan 2016

Fingerprint

Authentication
Cryptography
Field programmable gate arrays (FPGA)
Light emitting diodes
Hardware
Controllers
Networks (circuits)
Computer hardware
Clocks
Throughput
Polynomials

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

Cite this

@article{66728826c7b84d56a5953952f1374a2e,
title = "Reusable data-path architecture for encryption-then-authentication on FPGA",
abstract = "This paper proposes reusable data-path architecture for lightweight cryptography algorithms, reusing some similar hardware components for both encryption and authentication. In addition to efforts by many researches to optimize hardware architectures, to reduce hardware resources, our proposal is to reuse identical functional blocks within crypto-algorithms targeting for more secure cryptography like Message Authentication Code (MAC), authenticated encryption such as Encrypt-then-MAC (EtM) on Field Programmable Gate Arrays (FPGA). For this proposed reusable data-path, we have chosen LED algorithm for encryption and then PHOTON to generate the MAC code. Instead of creating two different circuits, one for PHOTON and another for LED, our proposal’s is to reuse some of identical block functions repeatedly, therefore reduce the size of required circuit area. Reuse of resources or identical functions however require controllers that enable sharing of data path that can also has different “rounds” of transforms required for different modes either PHOTON or LED in this case, in addition to controllers for individual algorithm. Also to enable comparable computation speed, the data-path has to be further refined, an improvement needed at least on par or better than the current techniques. For PHOTON data-path, we have improved performance of Mix-Columns, focusing on lengthy clock cycle of Galois polynomial multiplication. The results show that this proposed EtM hardware architecture achieves significant improvements, up to 587 MHz, 1336 Mbps and 3.2 Mbps/slices, for maximum frequency, throughput and efficiency, respectively.",
author = "Abbas, {Yasir Amer} and Razali Jidin and Norziana Jamil and Zaba, {Muhammad Reza}",
year = "2016",
month = "1",
day = "1",
doi = "10.15866/irecos.v11i1.8367",
language = "English",
volume = "11",
pages = "56--63",
journal = "International Review on Computers and Software",
issn = "1828-6003",
publisher = "Praise Worthy Prize",
number = "1",

}

Reusable data-path architecture for encryption-then-authentication on FPGA. / Abbas, Yasir Amer; Jidin, Razali; Jamil, Norziana; Zaba, Muhammad Reza.

In: International Review on Computers and Software, Vol. 11, No. 1, 01.01.2016, p. 56-63.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Reusable data-path architecture for encryption-then-authentication on FPGA

AU - Abbas, Yasir Amer

AU - Jidin, Razali

AU - Jamil, Norziana

AU - Zaba, Muhammad Reza

PY - 2016/1/1

Y1 - 2016/1/1

N2 - This paper proposes reusable data-path architecture for lightweight cryptography algorithms, reusing some similar hardware components for both encryption and authentication. In addition to efforts by many researches to optimize hardware architectures, to reduce hardware resources, our proposal is to reuse identical functional blocks within crypto-algorithms targeting for more secure cryptography like Message Authentication Code (MAC), authenticated encryption such as Encrypt-then-MAC (EtM) on Field Programmable Gate Arrays (FPGA). For this proposed reusable data-path, we have chosen LED algorithm for encryption and then PHOTON to generate the MAC code. Instead of creating two different circuits, one for PHOTON and another for LED, our proposal’s is to reuse some of identical block functions repeatedly, therefore reduce the size of required circuit area. Reuse of resources or identical functions however require controllers that enable sharing of data path that can also has different “rounds” of transforms required for different modes either PHOTON or LED in this case, in addition to controllers for individual algorithm. Also to enable comparable computation speed, the data-path has to be further refined, an improvement needed at least on par or better than the current techniques. For PHOTON data-path, we have improved performance of Mix-Columns, focusing on lengthy clock cycle of Galois polynomial multiplication. The results show that this proposed EtM hardware architecture achieves significant improvements, up to 587 MHz, 1336 Mbps and 3.2 Mbps/slices, for maximum frequency, throughput and efficiency, respectively.

AB - This paper proposes reusable data-path architecture for lightweight cryptography algorithms, reusing some similar hardware components for both encryption and authentication. In addition to efforts by many researches to optimize hardware architectures, to reduce hardware resources, our proposal is to reuse identical functional blocks within crypto-algorithms targeting for more secure cryptography like Message Authentication Code (MAC), authenticated encryption such as Encrypt-then-MAC (EtM) on Field Programmable Gate Arrays (FPGA). For this proposed reusable data-path, we have chosen LED algorithm for encryption and then PHOTON to generate the MAC code. Instead of creating two different circuits, one for PHOTON and another for LED, our proposal’s is to reuse some of identical block functions repeatedly, therefore reduce the size of required circuit area. Reuse of resources or identical functions however require controllers that enable sharing of data path that can also has different “rounds” of transforms required for different modes either PHOTON or LED in this case, in addition to controllers for individual algorithm. Also to enable comparable computation speed, the data-path has to be further refined, an improvement needed at least on par or better than the current techniques. For PHOTON data-path, we have improved performance of Mix-Columns, focusing on lengthy clock cycle of Galois polynomial multiplication. The results show that this proposed EtM hardware architecture achieves significant improvements, up to 587 MHz, 1336 Mbps and 3.2 Mbps/slices, for maximum frequency, throughput and efficiency, respectively.

UR - http://www.scopus.com/inward/record.url?scp=84964207167&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84964207167&partnerID=8YFLogxK

U2 - 10.15866/irecos.v11i1.8367

DO - 10.15866/irecos.v11i1.8367

M3 - Article

VL - 11

SP - 56

EP - 63

JO - International Review on Computers and Software

JF - International Review on Computers and Software

SN - 1828-6003

IS - 1

ER -