Emerging hybrid chips containing both CPU and field-programmable gate array (FPGA) components are an exciting new development that promises COTS economies of scale, while also supporting hardware customization. However, current hybrid computational models are still immature, generally treating FPGAs as computational accelerators that are invoked passively as subroutines, or for essentially independent portions of a data flow computation, requiring only input and output queues. Effectively programming across the FPGA-CPU boundary will require a high-level programming model that abstracts the FPGA and CPU components, bus structure, memory, and low-level peripheral protocols into a transparent computational platform. The multithreaded shared-memory model has potential for this application. With this model, system developers can specify applications as sets of threads distributed flexibly across the system's CPU and FPGA assets.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering