Programming models for hybrid FPGA-CPU computational components: A missing link

David Andrews, Douglas Niehaus, Razali Jidin, Michael Finley, Wesley Peck, Michael Frisbie, Jorge Ortiz, Ed Komp, Peter Ashenden

Research output: Contribution to journalArticle

78 Citations (Scopus)

Abstract

Emerging hybrid chips containing both CPU and field-programmable gate array (FPGA) components are an exciting new development that promises COTS economies of scale, while also supporting hardware customization. However, current hybrid computational models are still immature, generally treating FPGAs as computational accelerators that are invoked passively as subroutines, or for essentially independent portions of a data flow computation, requiring only input and output queues. Effectively programming across the FPGA-CPU boundary will require a high-level programming model that abstracts the FPGA and CPU components, bus structure, memory, and low-level peripheral protocols into a transparent computational platform. The multithreaded shared-memory model has potential for this application. With this model, system developers can specify applications as sets of threads distributed flexibly across the system's CPU and FPGA assets.

Original languageEnglish
Pages (from-to)42-53
Number of pages12
JournalIEEE Micro
Volume24
Issue number4
DOIs
Publication statusPublished - 01 Jul 2004

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Andrews, D., Niehaus, D., Jidin, R., Finley, M., Peck, W., Frisbie, M., Ortiz, J., Komp, E., & Ashenden, P. (2004). Programming models for hybrid FPGA-CPU computational components: A missing link. IEEE Micro, 24(4), 42-53. https://doi.org/10.1109/MM.2004.36