Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling

Z. A. Noor Faizah, Ibrahim Ahmad, Pin Jern Ker, Y. Siti Munirah, R. Mohd Firdaus, E. Md Fazle, P. S. Menon

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively.

Original languageEnglish
Article number01017
JournalMATEC Web of Conferences
Volume78
DOIs
Publication statusPublished - 07 Oct 2016
Event2nd International Conference on Green Design and Manufacture, IConGDM 2016 - Phuket, Thailand
Duration: 01 May 201602 May 2016

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Transistors
Hafnium
Metals
Tungsten
Taguchi methods
Titanium
Fabrication
thiazole-4-carboxamide adenine dinucleotide
titanium silicide

All Science Journal Classification (ASJC) codes

  • Chemistry(all)
  • Materials Science(all)
  • Engineering(all)

Cite this

Noor Faizah, Z. A. ; Ahmad, Ibrahim ; Ker, Pin Jern ; Siti Munirah, Y. ; Mohd Firdaus, R. ; Md Fazle, E. ; Menon, P. S. / Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling. In: MATEC Web of Conferences. 2016 ; Vol. 78.
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abstract = "This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively.",
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Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling. / Noor Faizah, Z. A.; Ahmad, Ibrahim; Ker, Pin Jern; Siti Munirah, Y.; Mohd Firdaus, R.; Md Fazle, E.; Menon, P. S.

In: MATEC Web of Conferences, Vol. 78, 01017, 07.10.2016.

Research output: Contribution to journalConference article

TY - JOUR

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AU - Noor Faizah, Z. A.

AU - Ahmad, Ibrahim

AU - Ker, Pin Jern

AU - Siti Munirah, Y.

AU - Mohd Firdaus, R.

AU - Md Fazle, E.

AU - Menon, P. S.

PY - 2016/10/7

Y1 - 2016/10/7

N2 - This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively.

AB - This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively.

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