This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively.
|Journal||MATEC Web of Conferences|
|Publication status||Published - 07 Oct 2016|
|Event||2nd International Conference on Green Design and Manufacture, IConGDM 2016 - Phuket, Thailand|
Duration: 01 May 2016 → 02 May 2016
All Science Journal Classification (ASJC) codes
- Materials Science(all)