Performance analysis of full adder (FA) cells

Phuong Thi Yen, Noor Faizah Zainul Abidin, Azrul Ghazali

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Since full adders play a vital role in electronics design, new ideas, investigations and study cases for constructing full-adders are required. This paper presents a comprehensive study of 24 different single-bit full adder (FA) topologies. All FA cells are designed using 0.18μm Silterra transistor models. Each FA cell is analyzed in terms of power and delay. The design and simulation of each FA cell are performed using Hspice simulator. The results of this paper are expected to assist designers to select the appropriate FA cell that meets their specific applications.

Original languageEnglish
Title of host publicationISCI 2011 - 2011 IEEE Symposium on Computers and Informatics
Pages141-146
Number of pages6
DOIs
Publication statusPublished - 01 Sep 2011
Event2011 IEEE Symposium on Computers and Informatics, ISCI 2011 - Kuala Lumpur, Malaysia
Duration: 20 Mar 201122 Mar 2011

Publication series

NameISCI 2011 - 2011 IEEE Symposium on Computers and Informatics

Other

Other2011 IEEE Symposium on Computers and Informatics, ISCI 2011
CountryMalaysia
CityKuala Lumpur
Period20/03/1122/03/11

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All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Information Systems

Cite this

Yen, P. T., Abidin, N. F. Z., & Ghazali, A. (2011). Performance analysis of full adder (FA) cells. In ISCI 2011 - 2011 IEEE Symposium on Computers and Informatics (pp. 141-146). [5958899] (ISCI 2011 - 2011 IEEE Symposium on Computers and Informatics). https://doi.org/10.1109/ISCI.2011.5958899