Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array

F. Salehuddin, Ibrahim Ahmad, Fazrena Azlee Hamid, A. Zaharim, Afifah Maheran A. Hamid, P. Susthitha Menon, H. A. Elgomati, B. Yeop Majlis, P. R. Apte

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

In this study, orthogonal array of L18 in Taguchi method was used to optimize the process parameters variance on threshold voltage (V TH) in 45nm p-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to study the performance characteristics of the PMOS device. There are eight process parameters (control factors) were varied for 2 and 3 levels to performed 18 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with L 18 Orthogonal Array to aid in design and optimize the process parameters. The predicted values of the process parameters were verified successfully with ATHENA and ATLAS's simulator. In PMOS device, VTH implant dose (26%) and compensate implant dose (26%) were the major factors affecting the threshold voltage. While S/D Implant was identified as an adjustment factor in PMOS device. These adjustment factors have been used to get the nominal values of threshold voltage for PMOS device closer to -0.289V.

Original languageEnglish
Title of host publication2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings
Pages219-223
Number of pages5
DOIs
Publication statusPublished - 01 Dec 2012
Event2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Kuala Lumpur, Malaysia
Duration: 19 Sep 201221 Sep 2012

Other

Other2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012
CountryMalaysia
CityKuala Lumpur
Period19/09/1221/09/12

Fingerprint

MOSFET devices
Simulators
Threshold voltage
Taguchi methods
Analysis of variance (ANOVA)
Signal to noise ratio
Experiments

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Salehuddin, F., Ahmad, I., Hamid, F. A., Zaharim, A., Hamid, A. M. A., Menon, P. S., ... Apte, P. R. (2012). Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array. In 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings (pp. 219-223). [6417127] https://doi.org/10.1109/SMElec.2012.6417127
Salehuddin, F. ; Ahmad, Ibrahim ; Hamid, Fazrena Azlee ; Zaharim, A. ; Hamid, Afifah Maheran A. ; Menon, P. Susthitha ; Elgomati, H. A. ; Majlis, B. Yeop ; Apte, P. R. / Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array. 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings. 2012. pp. 219-223
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abstract = "In this study, orthogonal array of L18 in Taguchi method was used to optimize the process parameters variance on threshold voltage (V TH) in 45nm p-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to study the performance characteristics of the PMOS device. There are eight process parameters (control factors) were varied for 2 and 3 levels to performed 18 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with L 18 Orthogonal Array to aid in design and optimize the process parameters. The predicted values of the process parameters were verified successfully with ATHENA and ATLAS's simulator. In PMOS device, VTH implant dose (26{\%}) and compensate implant dose (26{\%}) were the major factors affecting the threshold voltage. While S/D Implant was identified as an adjustment factor in PMOS device. These adjustment factors have been used to get the nominal values of threshold voltage for PMOS device closer to -0.289V.",
author = "F. Salehuddin and Ibrahim Ahmad and Hamid, {Fazrena Azlee} and A. Zaharim and Hamid, {Afifah Maheran A.} and Menon, {P. Susthitha} and Elgomati, {H. A.} and Majlis, {B. Yeop} and Apte, {P. R.}",
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Salehuddin, F, Ahmad, I, Hamid, FA, Zaharim, A, Hamid, AMA, Menon, PS, Elgomati, HA, Majlis, BY & Apte, PR 2012, Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array. in 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings., 6417127, pp. 219-223, 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012, Kuala Lumpur, Malaysia, 19/09/12. https://doi.org/10.1109/SMElec.2012.6417127

Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array. / Salehuddin, F.; Ahmad, Ibrahim; Hamid, Fazrena Azlee; Zaharim, A.; Hamid, Afifah Maheran A.; Menon, P. Susthitha; Elgomati, H. A.; Majlis, B. Yeop; Apte, P. R.

2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings. 2012. p. 219-223 6417127.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Hamid, Afifah Maheran A.

AU - Menon, P. Susthitha

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AU - Majlis, B. Yeop

AU - Apte, P. R.

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N2 - In this study, orthogonal array of L18 in Taguchi method was used to optimize the process parameters variance on threshold voltage (V TH) in 45nm p-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to study the performance characteristics of the PMOS device. There are eight process parameters (control factors) were varied for 2 and 3 levels to performed 18 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of VTH for every row of experiment. VTH results were used as the evaluation variable. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with L 18 Orthogonal Array to aid in design and optimize the process parameters. The predicted values of the process parameters were verified successfully with ATHENA and ATLAS's simulator. In PMOS device, VTH implant dose (26%) and compensate implant dose (26%) were the major factors affecting the threshold voltage. While S/D Implant was identified as an adjustment factor in PMOS device. These adjustment factors have been used to get the nominal values of threshold voltage for PMOS device closer to -0.289V.

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Salehuddin F, Ahmad I, Hamid FA, Zaharim A, Hamid AMA, Menon PS et al. Optimization of process parameter variation in 45nm p-channel MOSFET using L18 orthogonal array. In 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings. 2012. p. 219-223. 6417127 https://doi.org/10.1109/SMElec.2012.6417127