This study reports on an investigation of the effect and optimization of process parameter variability on poly sheet resistance (Rs) and leakage current (ILeak) in 45 nm PMOS device. The experimental studies were conducted under varying four process parameters, namely Halo implantation, Source/Drain Implantation, Oxide Growth Temperature and Silicide Anneal Temperature. Taguchi Method was used to determine the settings of process parameters. The level of importance of the process parameters on the poly sheet resistance and leakage current were determined by using Analysis of Variance (ANOVA). Virtual fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. The optimum process parameter combination was obtained by using the analysis of Signal-to-Noise (S/N) ratio. The confirmation tests indicated that it is possible to decrease the poly sheet resistance and leakage current significantly by using the Taguchi method. The results show that the Rs and ILeak after optimizations approaches are 67.53 Ω, sq-1 and 0.1850 m A μm-1, respectively. In this study, S/D implantation was identified as one of the process parameters that has the strongest effect on the response characteristics.
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