Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method

A. H. Afifah Maheran, P. S. Menon, Ibrahim Ahmad, S. Shaari

Research output: Contribution to journalConference article

9 Citations (Scopus)

Abstract

In this article, Taguchi orthogonal array method was used to optimize the process parameters during the design of a 22 nm n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in order to decrease the leakage current (ILEAK) of the device. Titanium dioxide (TiO2) was used as the dielectric layer to replace the traditional silicon dioxide SiO2 and tungsten silicide (WSix) was used as a metal gate to replace polysilicon. The device's fabrication and electrical characterization were executed using ATHENA and ATLAS modules from Silvaco International. Taguchi's Power of Three Series L9 orthogonal array was used to optimize the device process parameters and to finally predict the best process parameter combination to obtain the minimum leakage current (ILEAK) using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The optimization resulted in the attainment of the lowest ILEAK mean value of 0.25759 nA/μm which is in accordance to the predicted value given in the International Technology Roadmap for Semiconductors (ITRS) 2011.

Original languageEnglish
Pages (from-to)1-5
Number of pages5
JournalJurnal Teknologi (Sciences and Engineering)
Volume68
Issue number4
DOIs
Publication statusPublished - 01 Jan 2014
Event1st International Conference on Robust Quality Engineering, ICRQE 2013 - Kuala Lumpur, Malaysia
Duration: 24 Apr 201325 Apr 2013

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Taguchi methods
MOSFET devices
Leakage currents
Polysilicon
Titanium dioxide
Tungsten
Signal to noise ratio
Silica
Semiconductor materials
Fabrication
Metals

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

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abstract = "In this article, Taguchi orthogonal array method was used to optimize the process parameters during the design of a 22 nm n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in order to decrease the leakage current (ILEAK) of the device. Titanium dioxide (TiO2) was used as the dielectric layer to replace the traditional silicon dioxide SiO2 and tungsten silicide (WSix) was used as a metal gate to replace polysilicon. The device's fabrication and electrical characterization were executed using ATHENA and ATLAS modules from Silvaco International. Taguchi's Power of Three Series L9 orthogonal array was used to optimize the device process parameters and to finally predict the best process parameter combination to obtain the minimum leakage current (ILEAK) using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The optimization resulted in the attainment of the lowest ILEAK mean value of 0.25759 nA/μm which is in accordance to the predicted value given in the International Technology Roadmap for Semiconductors (ITRS) 2011.",
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Optimisation of process parameters for lower leakage current in 22 nm n-type MOSFET device using Taguchi method. / Afifah Maheran, A. H.; Menon, P. S.; Ahmad, Ibrahim; Shaari, S.

In: Jurnal Teknologi (Sciences and Engineering), Vol. 68, No. 4, 01.01.2014, p. 1-5.

Research output: Contribution to journalConference article

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AU - Afifah Maheran, A. H.

AU - Menon, P. S.

AU - Ahmad, Ibrahim

AU - Shaari, S.

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N2 - In this article, Taguchi orthogonal array method was used to optimize the process parameters during the design of a 22 nm n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in order to decrease the leakage current (ILEAK) of the device. Titanium dioxide (TiO2) was used as the dielectric layer to replace the traditional silicon dioxide SiO2 and tungsten silicide (WSix) was used as a metal gate to replace polysilicon. The device's fabrication and electrical characterization were executed using ATHENA and ATLAS modules from Silvaco International. Taguchi's Power of Three Series L9 orthogonal array was used to optimize the device process parameters and to finally predict the best process parameter combination to obtain the minimum leakage current (ILEAK) using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The optimization resulted in the attainment of the lowest ILEAK mean value of 0.25759 nA/μm which is in accordance to the predicted value given in the International Technology Roadmap for Semiconductors (ITRS) 2011.

AB - In this article, Taguchi orthogonal array method was used to optimize the process parameters during the design of a 22 nm n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in order to decrease the leakage current (ILEAK) of the device. Titanium dioxide (TiO2) was used as the dielectric layer to replace the traditional silicon dioxide SiO2 and tungsten silicide (WSix) was used as a metal gate to replace polysilicon. The device's fabrication and electrical characterization were executed using ATHENA and ATLAS modules from Silvaco International. Taguchi's Power of Three Series L9 orthogonal array was used to optimize the device process parameters and to finally predict the best process parameter combination to obtain the minimum leakage current (ILEAK) using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The optimization resulted in the attainment of the lowest ILEAK mean value of 0.25759 nA/μm which is in accordance to the predicted value given in the International Technology Roadmap for Semiconductors (ITRS) 2011.

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