Modelling of 14NM gate length La2O3-based n-type MOSFET

S. K. Mah, Ibrahim Ahmad, Pin Jern Ker, Z. A. Noor Faizah

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Gate length shrinkage is still the widely used method in transistor downsizing. In view of this, the downsizing of Equivalent Oxide Thickness (EOT) is also of high importance as it is the main focus in the process. Therefore, various studies on Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) fabricated from high-k dielectric and metal gate have been reported till today. In this paper, a 14nm silicon based n-type MOSFET was virtually fabricated using Lanthanum Oxide (La2O3) on Titanium Silicide (TiSi2). ATHENA and ATLAS modules from SILVACO were used for process and device simulation respectively. The results from this work show that the threshold voltage, VTH, on-current, ION and off-current, IOFF are 0.208397 V, 4.80048 x 10-5 A/μm and 1.00402 x 10-7 A/μm respectively. Furthermore, it is demonstrated that the development of high-k/metal gate MOSFET is a promising prospect for high performance nanoscale transistors.

Original languageEnglish
Pages (from-to)107-110
Number of pages4
JournalJournal of Telecommunication, Electronic and Computer Engineering
Volume8
Issue number4
Publication statusPublished - 01 Jan 2016

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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