Modeling, simulation and optimization of 14nm high-K/metal gate NMOS with taguchi method

S. K. Mah, Ibrahim Ahmad, Pin Jern Ker, K. P. Tan, Z. A.Noor Faizah

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The developments in electronics technology push the invention of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) towards smaller physical dimension with improvements in both quality and performance. In this paper, design, fabrication and simulation of electrical characteristics of 14nm La2O3/WSi2NMOS is presented. The fabrication and simulation process of device were performed by using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools, which consists of ATHENA and ATLAS. The designed device was optimized using Taguchi Method that involves orthogonal arrays and analysis of variance (ANOVA). The original results before optimization process for VTHis 0.212648V (7.5% lower than the targeted value) and IOFF is 3.73851×10-9 A/μm while the optimized results for VTH is 0.233321 V (1.44 % higher than the targeted value) and IOFFis 4.732375×10-11 A/Δm which fulfilled the targets based on International Technology Roadmap for Semiconductors (ITRS) 2013. The Taguchi optimization method yields a significantly lower IOFF with an improved ION/IOFF ratio by a factor of 25.

Original languageEnglish
Title of host publication2018 IEEE International Conference on Semiconductor Electronics, ICSE 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages275-278
Number of pages4
ISBN (Electronic)9781538652831
DOIs
Publication statusPublished - 03 Oct 2018
Event13th IEEE International Conference on Semiconductor Electronics, ICSE 2018 - Kuala Lumpur, Malaysia
Duration: 15 Aug 201817 Aug 2018

Publication series

NameIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
Volume2018-August

Other

Other13th IEEE International Conference on Semiconductor Electronics, ICSE 2018
CountryMalaysia
CityKuala Lumpur
Period15/08/1817/08/18

Fingerprint

Taguchi methods
Metals
Fabrication
Computer simulation
Patents and inventions
MOSFET devices
Analysis of variance (ANOVA)
Electronic equipment
Semiconductor materials

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Mah, S. K., Ahmad, I., Ker, P. J., Tan, K. P., & Faizah, Z. A. N. (2018). Modeling, simulation and optimization of 14nm high-K/metal gate NMOS with taguchi method. In 2018 IEEE International Conference on Semiconductor Electronics, ICSE 2018 - Proceedings (pp. 275-278). [8481293] (IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE; Vol. 2018-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SMELEC.2018.8481293
Mah, S. K. ; Ahmad, Ibrahim ; Ker, Pin Jern ; Tan, K. P. ; Faizah, Z. A.Noor. / Modeling, simulation and optimization of 14nm high-K/metal gate NMOS with taguchi method. 2018 IEEE International Conference on Semiconductor Electronics, ICSE 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 275-278 (IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE).
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abstract = "The developments in electronics technology push the invention of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) towards smaller physical dimension with improvements in both quality and performance. In this paper, design, fabrication and simulation of electrical characteristics of 14nm La2O3/WSi2NMOS is presented. The fabrication and simulation process of device were performed by using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools, which consists of ATHENA and ATLAS. The designed device was optimized using Taguchi Method that involves orthogonal arrays and analysis of variance (ANOVA). The original results before optimization process for VTHis 0.212648V (7.5{\%} lower than the targeted value) and IOFF is 3.73851×10-9 A/μm while the optimized results for VTH is 0.233321 V (1.44 {\%} higher than the targeted value) and IOFFis 4.732375×10-11 A/Δm which fulfilled the targets based on International Technology Roadmap for Semiconductors (ITRS) 2013. The Taguchi optimization method yields a significantly lower IOFF with an improved ION/IOFF ratio by a factor of 25.",
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Mah, SK, Ahmad, I, Ker, PJ, Tan, KP & Faizah, ZAN 2018, Modeling, simulation and optimization of 14nm high-K/metal gate NMOS with taguchi method. in 2018 IEEE International Conference on Semiconductor Electronics, ICSE 2018 - Proceedings., 8481293, IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE, vol. 2018-August, Institute of Electrical and Electronics Engineers Inc., pp. 275-278, 13th IEEE International Conference on Semiconductor Electronics, ICSE 2018, Kuala Lumpur, Malaysia, 15/08/18. https://doi.org/10.1109/SMELEC.2018.8481293

Modeling, simulation and optimization of 14nm high-K/metal gate NMOS with taguchi method. / Mah, S. K.; Ahmad, Ibrahim; Ker, Pin Jern; Tan, K. P.; Faizah, Z. A.Noor.

2018 IEEE International Conference on Semiconductor Electronics, ICSE 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 275-278 8481293 (IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE; Vol. 2018-August).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Mah SK, Ahmad I, Ker PJ, Tan KP, Faizah ZAN. Modeling, simulation and optimization of 14nm high-K/metal gate NMOS with taguchi method. In 2018 IEEE International Conference on Semiconductor Electronics, ICSE 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 275-278. 8481293. (IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE). https://doi.org/10.1109/SMELEC.2018.8481293