Modeling of 14 nm gate length n-Type MOSFET

Z. A.Noor Faizah, Ibrahim Ahmad, Pin Jern Ker, P. S.Akmaa Roslan, A. H.Afifah Maheran

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Metal-Oxide-Semiconductor Field Effect Transistors MOSFETs (MOSFETs) transistor have been scaled tremendously through Moore's Law since 1974 in order to compact transistors in a single chip. Thus, a proper scaling technique is compulsory to minimize the short channel effect (SCE) problems. In this paper, the virtual fabricated design and device's characterization of 14 nm HfO2/WSi2 n-type MOSFET device is presented. The device is scaled based on previous research on 32 nm transistors. The virtual fabrication and simulation of n-type MOSFETs are implemented using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools named ATHENA and ATLAS. From the simulation, result shows that the optimal value of threshold voltage (VTH), drive current (ION) and leakage current (IOFF) are 0.232291 V, 78.922×10-6 A/um and 77.11×10-9 A/um respectively. These simulation results are believed to be able to create a touchstone towards the optimization and fabrication of 14 nm device's gate length utilizing High-K/Metal Gate n-type MOSFET in impending work.

Original languageEnglish
Title of host publicationRSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479985500
DOIs
Publication statusPublished - 11 Dec 2015
Event10th IEEE Regional Symposium on Micro and Nano Electronics, RSM 2015 - Kuala Terengganu, Malaysia
Duration: 19 Aug 201521 Aug 2015

Publication series

NameRSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings

Other

Other10th IEEE Regional Symposium on Micro and Nano Electronics, RSM 2015
CountryMalaysia
CityKuala Terengganu
Period19/08/1521/08/15

Fingerprint

Transistors
field effect transistors
MOSFET devices
Fabrication
transistors
Threshold voltage
Leakage currents
fabrication
Metals
simulation
metal oxide semiconductors
threshold voltage
leakage
chips
wafers
scaling
optimization
metals
thiazole-4-carboxamide adenine dinucleotide

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Instrumentation
  • Electrical and Electronic Engineering

Cite this

Faizah, Z. A. N., Ahmad, I., Ker, P. J., Roslan, P. S. A., & Maheran, A. H. A. (2015). Modeling of 14 nm gate length n-Type MOSFET. In RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings [7354988] (RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RSM.2015.7354988
Faizah, Z. A.Noor ; Ahmad, Ibrahim ; Ker, Pin Jern ; Roslan, P. S.Akmaa ; Maheran, A. H.Afifah. / Modeling of 14 nm gate length n-Type MOSFET. RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. (RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings).
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Faizah, ZAN, Ahmad, I, Ker, PJ, Roslan, PSA & Maheran, AHA 2015, Modeling of 14 nm gate length n-Type MOSFET. in RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings., 7354988, RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings, Institute of Electrical and Electronics Engineers Inc., 10th IEEE Regional Symposium on Micro and Nano Electronics, RSM 2015, Kuala Terengganu, Malaysia, 19/08/15. https://doi.org/10.1109/RSM.2015.7354988

Modeling of 14 nm gate length n-Type MOSFET. / Faizah, Z. A.Noor; Ahmad, Ibrahim; Ker, Pin Jern; Roslan, P. S.Akmaa; Maheran, A. H.Afifah.

RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. 7354988 (RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Faizah, Z. A.Noor

AU - Ahmad, Ibrahim

AU - Ker, Pin Jern

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AU - Maheran, A. H.Afifah

PY - 2015/12/11

Y1 - 2015/12/11

N2 - Metal-Oxide-Semiconductor Field Effect Transistors MOSFETs (MOSFETs) transistor have been scaled tremendously through Moore's Law since 1974 in order to compact transistors in a single chip. Thus, a proper scaling technique is compulsory to minimize the short channel effect (SCE) problems. In this paper, the virtual fabricated design and device's characterization of 14 nm HfO2/WSi2 n-type MOSFET device is presented. The device is scaled based on previous research on 32 nm transistors. The virtual fabrication and simulation of n-type MOSFETs are implemented using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools named ATHENA and ATLAS. From the simulation, result shows that the optimal value of threshold voltage (VTH), drive current (ION) and leakage current (IOFF) are 0.232291 V, 78.922×10-6 A/um and 77.11×10-9 A/um respectively. These simulation results are believed to be able to create a touchstone towards the optimization and fabrication of 14 nm device's gate length utilizing High-K/Metal Gate n-type MOSFET in impending work.

AB - Metal-Oxide-Semiconductor Field Effect Transistors MOSFETs (MOSFETs) transistor have been scaled tremendously through Moore's Law since 1974 in order to compact transistors in a single chip. Thus, a proper scaling technique is compulsory to minimize the short channel effect (SCE) problems. In this paper, the virtual fabricated design and device's characterization of 14 nm HfO2/WSi2 n-type MOSFET device is presented. The device is scaled based on previous research on 32 nm transistors. The virtual fabrication and simulation of n-type MOSFETs are implemented using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools named ATHENA and ATLAS. From the simulation, result shows that the optimal value of threshold voltage (VTH), drive current (ION) and leakage current (IOFF) are 0.232291 V, 78.922×10-6 A/um and 77.11×10-9 A/um respectively. These simulation results are believed to be able to create a touchstone towards the optimization and fabrication of 14 nm device's gate length utilizing High-K/Metal Gate n-type MOSFET in impending work.

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M3 - Conference contribution

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BT - RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Faizah ZAN, Ahmad I, Ker PJ, Roslan PSA, Maheran AHA. Modeling of 14 nm gate length n-Type MOSFET. In RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2015. 7354988. (RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings). https://doi.org/10.1109/RSM.2015.7354988