Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method

Husam Ahmed Elgomati, Burhanuddin Yeop Majlis, Ibrahim Ahmad

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilicon thickness and silicide annealing time. The setting of process parameters were determined by Taguchi method L18 experimental design. From there, the level of importance of each of the process parameters on threshold voltage was determined using analysis of variance (ANOVA). Transistor fabrication was performed by using Silvaco ATHENA module. Silvaco ATLAS module takes care of electrical characterization for the device. These two simulators results were analyzed with Taguchi method to aid in design and optimizing process parameters. Threshold voltage (VTH) results were used as the evaluation parameters. The results show that the VTH value 0.1099 V for NMOS can be achieved respectively, much closer to the ITRS prediction than our previous L9 experiment result. As the conclusion, by utilizing L18 Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.1099 V that is well within ITRS 2003 prediction for 32nm transistor

Original languageEnglish
Title of host publicationInternational Conference on Fundamental and Applied Sciences 2012, ICFAS 2012
Pages543-549
Number of pages7
Volume1482
DOIs
Publication statusPublished - 01 Dec 2012
Event2nd International Conference on Fundamental and Applied Sciences 2012, ICFAS 2012 - Kuala Lumpur, Malaysia
Duration: 12 Jun 201214 Jun 2012

Other

Other2nd International Conference on Fundamental and Applied Sciences 2012, ICFAS 2012
CountryMalaysia
CityKuala Lumpur
Period12/06/1214/06/12

Fingerprint

Taguchi methods
threshold voltage
transistors
implantation
modules
analysis of variance
fabrication
predictions
simulators
CMOS
adjusting
annealing
evaluation

All Science Journal Classification (ASJC) codes

  • Physics and Astronomy(all)

Cite this

Elgomati, H. A., Majlis, B. Y., & Ahmad, I. (2012). Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method. In International Conference on Fundamental and Applied Sciences 2012, ICFAS 2012 (Vol. 1482, pp. 543-549) https://doi.org/10.1063/1.4757531
Elgomati, Husam Ahmed ; Majlis, Burhanuddin Yeop ; Ahmad, Ibrahim. / Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method. International Conference on Fundamental and Applied Sciences 2012, ICFAS 2012. Vol. 1482 2012. pp. 543-549
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Elgomati, HA, Majlis, BY & Ahmad, I 2012, Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method. in International Conference on Fundamental and Applied Sciences 2012, ICFAS 2012. vol. 1482, pp. 543-549, 2nd International Conference on Fundamental and Applied Sciences 2012, ICFAS 2012, Kuala Lumpur, Malaysia, 12/06/12. https://doi.org/10.1063/1.4757531

Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method. / Elgomati, Husam Ahmed; Majlis, Burhanuddin Yeop; Ahmad, Ibrahim.

International Conference on Fundamental and Applied Sciences 2012, ICFAS 2012. Vol. 1482 2012. p. 543-549.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Elgomati HA, Majlis BY, Ahmad I. Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method. In International Conference on Fundamental and Applied Sciences 2012, ICFAS 2012. Vol. 1482. 2012. p. 543-549 https://doi.org/10.1063/1.4757531