Low complexity multidimensional CDF 5/3 DWT architecture

Saad Al-Azawi, Yasir Amer Abbas, Razali Jidin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper introduces an efficient low complexity multidimensional DWT architecture. The proposed architecture is based on a lifting-scheme for the Cohen-Daubechies-Feauveau (CDF) 5/3 DWT filter. It consists of low complexity identical computation and control units which can be used easily to implement 2-D and 3-D DWT architectures. The synthesis results show that the output latency is 2N+2 clock cycles, with N2+2N+2 clock cycles required for the first level 2-D CDF 5/3 DWT computation. The architecture is parameterized to tackle various images and wordlength sizes. Furthermore, the proposed architecture is implemented using a Virtex 6 Xilinx FPGA platform. The implementation results reveal that the proposed architecture can operate at up to 198 MHz operating frequency. This reduces the time for first level DWT decomposition of a 512×512-pixel image to less than 1.3 m sec.

Original languageEnglish
Title of host publication2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages804-808
Number of pages5
ISBN (Electronic)9781479925810
DOIs
Publication statusPublished - 14 Oct 2014
Event2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014 - Manchester, United Kingdom
Duration: 23 Jul 201425 Jul 2014

Other

Other2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014
CountryUnited Kingdom
CityManchester
Period23/07/1425/07/14

Fingerprint

Clocks
Field programmable gate arrays (FPGA)
Pixels
Decomposition

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Signal Processing

Cite this

Al-Azawi, S., Abbas, Y. A., & Jidin, R. (2014). Low complexity multidimensional CDF 5/3 DWT architecture. In 2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014 (pp. 804-808). [6923937] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CSNDSP.2014.6923937
Al-Azawi, Saad ; Abbas, Yasir Amer ; Jidin, Razali. / Low complexity multidimensional CDF 5/3 DWT architecture. 2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 804-808
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Al-Azawi, S, Abbas, YA & Jidin, R 2014, Low complexity multidimensional CDF 5/3 DWT architecture. in 2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014., 6923937, Institute of Electrical and Electronics Engineers Inc., pp. 804-808, 2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014, Manchester, United Kingdom, 23/07/14. https://doi.org/10.1109/CSNDSP.2014.6923937

Low complexity multidimensional CDF 5/3 DWT architecture. / Al-Azawi, Saad; Abbas, Yasir Amer; Jidin, Razali.

2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 804-808 6923937.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Al-Azawi S, Abbas YA, Jidin R. Low complexity multidimensional CDF 5/3 DWT architecture. In 2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 804-808. 6923937 https://doi.org/10.1109/CSNDSP.2014.6923937