Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device

Norani Atan, Ibrahim Ahmad, Burhanuddin Bin Yeop Majlis, Izzati Binti Ahmad Fauzi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The process parameters are very crucial factor in the development of transistors. There are many process parameters that influenced in the development of the transistors. In this research, we investigate the effects of the process parameters variation on response characteristics such as threshold voltage (V TH ) and sub-threshold leakage current (I OFF ) in 18nm NMOS device. The technique to identify semiconductor process parameters whose variability would impact most on the device characteristic is realized through the process by using Taguchi robust design method. This paper presents the process parameters that influenced in threshold voltage (V TH ) and sub-threshold leakage current (I OFF ) which includes the Halo Implantation, Compensation Implantation, Adjustment Threshold voltage Implantation and Source/Drain Implantation. The design, fabrication and characterization of 18nm HfO 2 /TiSi 2 NMOS device is simulated and performed via a tool called Virtual Wafer Fabrication (VWF) Silvaco TCAD Tool known as ATHENA and ATLAS simulators. These two simulators were combined with Taguchi L9 Orthogonal method to aid in the design and the optimization of the process parameters to achieve the optimum average of threshold voltage (V TH ) and sub-threshold leakage current, (I OFF ) in 18nm device. Results from this research were obtained; where Halo Implantation dose was identified as one of the process parameter that has the strongest effect on the response characteristics. Whereby the Compensation Implantation dose was identified as an adjustment factor to get the nominal values of threshold voltage V TH , and sub-threshold leakage current, I OFF for 18nm NMOS devices equal to 0.302849 volts and 1.9123×10 -16 A/μm respectively. The design values are referred to ITRS 2011 prediction.

Original languageEnglish
Title of host publicationNational Physics Conference 2014, PERFIK 2014
EditorsThian-Khok Yong, Yeong-Nan Phua, Horng-Sheng Lin, Faidz Abd Rahman
PublisherAmerican Institute of Physics Inc.
ISBN (Electronic)9780735412996
DOIs
Publication statusPublished - 24 Apr 2015
EventNational Physics Conference 2014, PERFIK 2014 - Kuala Lumpur, Malaysia
Duration: 18 Nov 201419 Nov 2014

Publication series

NameAIP Conference Proceedings
Volume1657
ISSN (Print)0094-243X
ISSN (Electronic)1551-7616

Other

OtherNational Physics Conference 2014, PERFIK 2014
CountryMalaysia
CityKuala Lumpur
Period18/11/1419/11/14

Fingerprint

threshold voltage
leakage
implantation
thresholds
semiconductors
simulators
dosage
halos
transistors
adjusting
simulator
methodology
fabrication
design optimization
prediction
parameter
design method
wafers
drain
aid

All Science Journal Classification (ASJC) codes

  • Ecology, Evolution, Behavior and Systematics
  • Ecology
  • Plant Science
  • Physics and Astronomy(all)
  • Nature and Landscape Conservation

Cite this

Atan, N., Ahmad, I., Majlis, B. B. Y., & Fauzi, I. B. A. (2015). Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device. In T-K. Yong, Y-N. Phua, H-S. Lin, & F. A. Rahman (Eds.), National Physics Conference 2014, PERFIK 2014 [110002] (AIP Conference Proceedings; Vol. 1657). American Institute of Physics Inc.. https://doi.org/10.1063/1.4915221
Atan, Norani ; Ahmad, Ibrahim ; Majlis, Burhanuddin Bin Yeop ; Fauzi, Izzati Binti Ahmad. / Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device. National Physics Conference 2014, PERFIK 2014. editor / Thian-Khok Yong ; Yeong-Nan Phua ; Horng-Sheng Lin ; Faidz Abd Rahman. American Institute of Physics Inc., 2015. (AIP Conference Proceedings).
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abstract = "The process parameters are very crucial factor in the development of transistors. There are many process parameters that influenced in the development of the transistors. In this research, we investigate the effects of the process parameters variation on response characteristics such as threshold voltage (V TH ) and sub-threshold leakage current (I OFF ) in 18nm NMOS device. The technique to identify semiconductor process parameters whose variability would impact most on the device characteristic is realized through the process by using Taguchi robust design method. This paper presents the process parameters that influenced in threshold voltage (V TH ) and sub-threshold leakage current (I OFF ) which includes the Halo Implantation, Compensation Implantation, Adjustment Threshold voltage Implantation and Source/Drain Implantation. The design, fabrication and characterization of 18nm HfO 2 /TiSi 2 NMOS device is simulated and performed via a tool called Virtual Wafer Fabrication (VWF) Silvaco TCAD Tool known as ATHENA and ATLAS simulators. These two simulators were combined with Taguchi L9 Orthogonal method to aid in the design and the optimization of the process parameters to achieve the optimum average of threshold voltage (V TH ) and sub-threshold leakage current, (I OFF ) in 18nm device. Results from this research were obtained; where Halo Implantation dose was identified as one of the process parameter that has the strongest effect on the response characteristics. Whereby the Compensation Implantation dose was identified as an adjustment factor to get the nominal values of threshold voltage V TH , and sub-threshold leakage current, I OFF for 18nm NMOS devices equal to 0.302849 volts and 1.9123×10 -16 A/μm respectively. The design values are referred to ITRS 2011 prediction.",
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Atan, N, Ahmad, I, Majlis, BBY & Fauzi, IBA 2015, Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device. in T-K Yong, Y-N Phua, H-S Lin & FA Rahman (eds), National Physics Conference 2014, PERFIK 2014., 110002, AIP Conference Proceedings, vol. 1657, American Institute of Physics Inc., National Physics Conference 2014, PERFIK 2014, Kuala Lumpur, Malaysia, 18/11/14. https://doi.org/10.1063/1.4915221

Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device. / Atan, Norani; Ahmad, Ibrahim; Majlis, Burhanuddin Bin Yeop; Fauzi, Izzati Binti Ahmad.

National Physics Conference 2014, PERFIK 2014. ed. / Thian-Khok Yong; Yeong-Nan Phua; Horng-Sheng Lin; Faidz Abd Rahman. American Institute of Physics Inc., 2015. 110002 (AIP Conference Proceedings; Vol. 1657).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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T1 - Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device

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AU - Ahmad, Ibrahim

AU - Majlis, Burhanuddin Bin Yeop

AU - Fauzi, Izzati Binti Ahmad

PY - 2015/4/24

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N2 - The process parameters are very crucial factor in the development of transistors. There are many process parameters that influenced in the development of the transistors. In this research, we investigate the effects of the process parameters variation on response characteristics such as threshold voltage (V TH ) and sub-threshold leakage current (I OFF ) in 18nm NMOS device. The technique to identify semiconductor process parameters whose variability would impact most on the device characteristic is realized through the process by using Taguchi robust design method. This paper presents the process parameters that influenced in threshold voltage (V TH ) and sub-threshold leakage current (I OFF ) which includes the Halo Implantation, Compensation Implantation, Adjustment Threshold voltage Implantation and Source/Drain Implantation. The design, fabrication and characterization of 18nm HfO 2 /TiSi 2 NMOS device is simulated and performed via a tool called Virtual Wafer Fabrication (VWF) Silvaco TCAD Tool known as ATHENA and ATLAS simulators. These two simulators were combined with Taguchi L9 Orthogonal method to aid in the design and the optimization of the process parameters to achieve the optimum average of threshold voltage (V TH ) and sub-threshold leakage current, (I OFF ) in 18nm device. Results from this research were obtained; where Halo Implantation dose was identified as one of the process parameter that has the strongest effect on the response characteristics. Whereby the Compensation Implantation dose was identified as an adjustment factor to get the nominal values of threshold voltage V TH , and sub-threshold leakage current, I OFF for 18nm NMOS devices equal to 0.302849 volts and 1.9123×10 -16 A/μm respectively. The design values are referred to ITRS 2011 prediction.

AB - The process parameters are very crucial factor in the development of transistors. There are many process parameters that influenced in the development of the transistors. In this research, we investigate the effects of the process parameters variation on response characteristics such as threshold voltage (V TH ) and sub-threshold leakage current (I OFF ) in 18nm NMOS device. The technique to identify semiconductor process parameters whose variability would impact most on the device characteristic is realized through the process by using Taguchi robust design method. This paper presents the process parameters that influenced in threshold voltage (V TH ) and sub-threshold leakage current (I OFF ) which includes the Halo Implantation, Compensation Implantation, Adjustment Threshold voltage Implantation and Source/Drain Implantation. The design, fabrication and characterization of 18nm HfO 2 /TiSi 2 NMOS device is simulated and performed via a tool called Virtual Wafer Fabrication (VWF) Silvaco TCAD Tool known as ATHENA and ATLAS simulators. These two simulators were combined with Taguchi L9 Orthogonal method to aid in the design and the optimization of the process parameters to achieve the optimum average of threshold voltage (V TH ) and sub-threshold leakage current, (I OFF ) in 18nm device. Results from this research were obtained; where Halo Implantation dose was identified as one of the process parameter that has the strongest effect on the response characteristics. Whereby the Compensation Implantation dose was identified as an adjustment factor to get the nominal values of threshold voltage V TH , and sub-threshold leakage current, I OFF for 18nm NMOS devices equal to 0.302849 volts and 1.9123×10 -16 A/μm respectively. The design values are referred to ITRS 2011 prediction.

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A2 - Phua, Yeong-Nan

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Atan N, Ahmad I, Majlis BBY, Fauzi IBA. Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device. In Yong T-K, Phua Y-N, Lin H-S, Rahman FA, editors, National Physics Conference 2014, PERFIK 2014. American Institute of Physics Inc. 2015. 110002. (AIP Conference Proceedings). https://doi.org/10.1063/1.4915221