Influence of Optimization of Process Parameters on Threshold Voltage for Development of HfO2/TiSi2 18 nm PMOS

Norani Atan, Ibrahim Ahmad, B. Y. Majlis, M. F. Azle

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

Manufacturing a 18-nm transistor requires a variety of parameters, materials, temperatures, and methods. In this research, HfO2 was used as the gate dielectric ad TiO2 was used as the gate material. The transistor HfO2/TiSi2 18-nm PMOS was invented using SILVACO TCAD. Ion implantation was adopted in the fabrication process for the method's practicality and ability to be used to suppress short channel effects. The study involved ion implantation methods: compensation implantation, halo implantation energy, halo tilt, and source-drain implantation. Taguchi method is the best optimization process for a threshold voltage of HfO2/TiSi2 18-nm PMOS. In this case, the method adopted was Taguchi orthogonal array L9. The process parameters (ion implantations) and noise factors were evaluated by examining the Taguchi's signal-to-noise ratio (SNR) and nominal-the-best for the threshold voltage (VTH). After optimization, the result showed that the VTH value of the 18-nm PMOS device was-0.291339.

Original languageEnglish
Article number01019
JournalMATEC Web of Conferences
Volume78
DOIs
Publication statusPublished - 07 Oct 2016
Event2nd International Conference on Green Design and Manufacture, IConGDM 2016 - Phuket, Thailand
Duration: 01 May 201602 May 2016

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Threshold voltage
Ion implantation
Transistors
Taguchi methods
Gate dielectrics
Signal to noise ratio
Fabrication
Temperature

All Science Journal Classification (ASJC) codes

  • Chemistry(all)
  • Materials Science(all)
  • Engineering(all)

Cite this

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title = "Influence of Optimization of Process Parameters on Threshold Voltage for Development of HfO2/TiSi2 18 nm PMOS",
abstract = "Manufacturing a 18-nm transistor requires a variety of parameters, materials, temperatures, and methods. In this research, HfO2 was used as the gate dielectric ad TiO2 was used as the gate material. The transistor HfO2/TiSi2 18-nm PMOS was invented using SILVACO TCAD. Ion implantation was adopted in the fabrication process for the method's practicality and ability to be used to suppress short channel effects. The study involved ion implantation methods: compensation implantation, halo implantation energy, halo tilt, and source-drain implantation. Taguchi method is the best optimization process for a threshold voltage of HfO2/TiSi2 18-nm PMOS. In this case, the method adopted was Taguchi orthogonal array L9. The process parameters (ion implantations) and noise factors were evaluated by examining the Taguchi's signal-to-noise ratio (SNR) and nominal-the-best for the threshold voltage (VTH). After optimization, the result showed that the VTH value of the 18-nm PMOS device was-0.291339.",
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Influence of Optimization of Process Parameters on Threshold Voltage for Development of HfO2/TiSi2 18 nm PMOS. / Atan, Norani; Ahmad, Ibrahim; Majlis, B. Y.; Azle, M. F.

In: MATEC Web of Conferences, Vol. 78, 01019, 07.10.2016.

Research output: Contribution to journalConference article

TY - JOUR

T1 - Influence of Optimization of Process Parameters on Threshold Voltage for Development of HfO2/TiSi2 18 nm PMOS

AU - Atan, Norani

AU - Ahmad, Ibrahim

AU - Majlis, B. Y.

AU - Azle, M. F.

PY - 2016/10/7

Y1 - 2016/10/7

N2 - Manufacturing a 18-nm transistor requires a variety of parameters, materials, temperatures, and methods. In this research, HfO2 was used as the gate dielectric ad TiO2 was used as the gate material. The transistor HfO2/TiSi2 18-nm PMOS was invented using SILVACO TCAD. Ion implantation was adopted in the fabrication process for the method's practicality and ability to be used to suppress short channel effects. The study involved ion implantation methods: compensation implantation, halo implantation energy, halo tilt, and source-drain implantation. Taguchi method is the best optimization process for a threshold voltage of HfO2/TiSi2 18-nm PMOS. In this case, the method adopted was Taguchi orthogonal array L9. The process parameters (ion implantations) and noise factors were evaluated by examining the Taguchi's signal-to-noise ratio (SNR) and nominal-the-best for the threshold voltage (VTH). After optimization, the result showed that the VTH value of the 18-nm PMOS device was-0.291339.

AB - Manufacturing a 18-nm transistor requires a variety of parameters, materials, temperatures, and methods. In this research, HfO2 was used as the gate dielectric ad TiO2 was used as the gate material. The transistor HfO2/TiSi2 18-nm PMOS was invented using SILVACO TCAD. Ion implantation was adopted in the fabrication process for the method's practicality and ability to be used to suppress short channel effects. The study involved ion implantation methods: compensation implantation, halo implantation energy, halo tilt, and source-drain implantation. Taguchi method is the best optimization process for a threshold voltage of HfO2/TiSi2 18-nm PMOS. In this case, the method adopted was Taguchi orthogonal array L9. The process parameters (ion implantations) and noise factors were evaluated by examining the Taguchi's signal-to-noise ratio (SNR) and nominal-the-best for the threshold voltage (VTH). After optimization, the result showed that the VTH value of the 18-nm PMOS device was-0.291339.

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