Implementing multi threaded system support for hybrid FPGA/CPU computational components

Razali Jidin, David Andrews, Douglas Niehaus

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Recently emerging hybrid chips containing both CPU's and FPGA components have the potential to enjoy significant economies of scale, while enabling system designers to include a significant amount of specialization within the FPGA component. However, realizing the promise of these new hybrid chips will require higher level programming models that support a far more integrated view of the CPU and FPGA components than is achievable with current methods. This paper describes the fundamental synchronization mechanisms, hardware interfaces and protocols that we are currently developing for extending the multi-threaded programming model across a CPU and FPGA. This work is a significant step in allowing programmer's access to the potential of FPGA based computations under a familiar programming model.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
EditorsT.P. Plaks
Pages116-122
Number of pages7
Publication statusPublished - 01 Dec 2004
EventProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 - Las Vegas, NV, United States
Duration: 21 Jun 200424 Jun 2004

Publication series

NameProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04

Other

OtherProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
CountryUnited States
CityLas Vegas, NV
Period21/06/0424/06/04

Fingerprint

Program processors
Field programmable gate arrays (FPGA)
Computer programming
Computer hardware
Interfaces (computer)
Synchronization
Network protocols

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Jidin, R., Andrews, D., & Niehaus, D. (2004). Implementing multi threaded system support for hybrid FPGA/CPU computational components. In T. P. Plaks (Ed.), Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 (pp. 116-122). (Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04).
Jidin, Razali ; Andrews, David ; Niehaus, Douglas. / Implementing multi threaded system support for hybrid FPGA/CPU computational components. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. editor / T.P. Plaks. 2004. pp. 116-122 (Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04).
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abstract = "Recently emerging hybrid chips containing both CPU's and FPGA components have the potential to enjoy significant economies of scale, while enabling system designers to include a significant amount of specialization within the FPGA component. However, realizing the promise of these new hybrid chips will require higher level programming models that support a far more integrated view of the CPU and FPGA components than is achievable with current methods. This paper describes the fundamental synchronization mechanisms, hardware interfaces and protocols that we are currently developing for extending the multi-threaded programming model across a CPU and FPGA. This work is a significant step in allowing programmer's access to the potential of FPGA based computations under a familiar programming model.",
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Jidin, R, Andrews, D & Niehaus, D 2004, Implementing multi threaded system support for hybrid FPGA/CPU computational components. in TP Plaks (ed.), Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04, pp. 116-122, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04, Las Vegas, NV, United States, 21/06/04.

Implementing multi threaded system support for hybrid FPGA/CPU computational components. / Jidin, Razali; Andrews, David; Niehaus, Douglas.

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. ed. / T.P. Plaks. 2004. p. 116-122 (Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Jidin R, Andrews D, Niehaus D. Implementing multi threaded system support for hybrid FPGA/CPU computational components. In Plaks TP, editor, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. 2004. p. 116-122. (Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04).