Impact of low-k devices on failure mode of flip chip tensile pull test

Zulkarnain Endut, Ibrahim Ahmad, Gary Lee How Swee, Norazham Mohd Sukemi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, the failure mode and solder bump strength for low-k flip chip devices were determined using die pull technique. The results show there is no significant difference between low-k and non low-k devices in terms of bumps strength for the amount of taffy in this device. However, there is different in failure mode which shows an increasing in VRO and SRO failure mode. Die pull test within a time and bake factor also help to minimize VRO and SRO failure mode. However, VRO and SRO failure mode were expected as an another impact of low-k materials on flip chip packaging.

Original languageEnglish
Title of host publication2006 International Conference on Electronic Materials and Packaging, EMAP
DOIs
Publication statusPublished - 01 Dec 2006
Event2006 International Conference on Electronic Materials and Packaging, EMAP - Kowloon, China
Duration: 11 Dec 200614 Dec 2006

Publication series

Name2006 International Conference on Electronic Materials and Packaging, EMAP

Other

Other2006 International Conference on Electronic Materials and Packaging, EMAP
CountryChina
CityKowloon
Period11/12/0614/12/06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • Cite this

    Endut, Z., Ahmad, I., Swee, G. L. H., & Sukemi, N. M. (2006). Impact of low-k devices on failure mode of flip chip tensile pull test. In 2006 International Conference on Electronic Materials and Packaging, EMAP [4430682] (2006 International Conference on Electronic Materials and Packaging, EMAP). https://doi.org/10.1109/EMAP.2006.4430682