Impact of HALO structure on threshold voltage and leakage current in 45nm NMOS device

F. Salehuddin, Ibrahim Ahmad, Fazrena Azlee Hamid, A. Zaharim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we investigate the impact of process parameter like halo structure on threshold voltage (VTH) and leakage current (I Leak) in 45nm NMOS device. The settings of process parameters were determined by using Taguchi experimental design method. Besides halo implant, the other process parameters which used were Source/Drain (S/D) implant and oxide growth temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to threshold voltage and leakage current are oxide growth temperature (71%) and S/D implant dose (47%) respectively. Whereas the second ranking factor affecting VTH and ILeak are halo implant tilt (15%) and halo implant dose (35%) respectively. As conclusions, S/D implant dose and oxide growth temperature have the strongest effect on the response characteristics. The results show that the VTH for NMOS device equal to 0.150V at tox= 1.1nm. The results show that ILeak after optimizations approaches is 51.8μA/m.

Original languageEnglish
Title of host publicationProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Pages1147-1150
Number of pages4
DOIs
Publication statusPublished - 01 Dec 2010
Event2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
Duration: 06 Dec 201009 Dec 2010

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
CountryMalaysia
CityKuala Lumpur
Period06/12/1009/12/10

Fingerprint

Threshold voltage
Leakage currents
Growth temperature
Simulators
Oxides
Taguchi methods
Design of experiments

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Salehuddin, F., Ahmad, I., Hamid, F. A., & Zaharim, A. (2010). Impact of HALO structure on threshold voltage and leakage current in 45nm NMOS device. In Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 (pp. 1147-1150). [5774934] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2010.5774934
Salehuddin, F. ; Ahmad, Ibrahim ; Hamid, Fazrena Azlee ; Zaharim, A. / Impact of HALO structure on threshold voltage and leakage current in 45nm NMOS device. Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. 2010. pp. 1147-1150 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).
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title = "Impact of HALO structure on threshold voltage and leakage current in 45nm NMOS device",
abstract = "In this paper, we investigate the impact of process parameter like halo structure on threshold voltage (VTH) and leakage current (I Leak) in 45nm NMOS device. The settings of process parameters were determined by using Taguchi experimental design method. Besides halo implant, the other process parameters which used were Source/Drain (S/D) implant and oxide growth temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to threshold voltage and leakage current are oxide growth temperature (71{\%}) and S/D implant dose (47{\%}) respectively. Whereas the second ranking factor affecting VTH and ILeak are halo implant tilt (15{\%}) and halo implant dose (35{\%}) respectively. As conclusions, S/D implant dose and oxide growth temperature have the strongest effect on the response characteristics. The results show that the VTH for NMOS device equal to 0.150V at tox= 1.1nm. The results show that ILeak after optimizations approaches is 51.8μA/m.",
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Salehuddin, F, Ahmad, I, Hamid, FA & Zaharim, A 2010, Impact of HALO structure on threshold voltage and leakage current in 45nm NMOS device. in Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010., 5774934, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 1147-1150, 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010, Kuala Lumpur, Malaysia, 06/12/10. https://doi.org/10.1109/APCCAS.2010.5774934

Impact of HALO structure on threshold voltage and leakage current in 45nm NMOS device. / Salehuddin, F.; Ahmad, Ibrahim; Hamid, Fazrena Azlee; Zaharim, A.

Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. 2010. p. 1147-1150 5774934 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Salehuddin F, Ahmad I, Hamid FA, Zaharim A. Impact of HALO structure on threshold voltage and leakage current in 45nm NMOS device. In Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. 2010. p. 1147-1150. 5774934. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2010.5774934