Enabling multithreading executions on the XILINX microkernel with a hardware scheduler

Yasmin Syuhada Harmin, Razali Jidin, Asraf Mohamed Moubark, Mohd Amiruddin Zainol

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multithreading programming can improve performance of an application especially to reduce processor busy waiting. Typically, threads that have to wait for input/output responses can wait in a queue (sleep queue), allowing other threads to utilize processor, therefore improving system timeliness and throughput. As such an application can be partitioned into several threads that can be executed on either single or multiple processors. Sharing of processors among threads however requires scheduling to ensure fair sharing scheme or to meet a specific execution objective. The scheduling mechanism serves to allocate which threads get to run on a processor alternately according to the adopted sharing scheme. Processor can be relieved of executing the required scheduling task if it can be performed by a hardware entity such as Field Programmable Gate Array (FPGA). This paper describes initial design of hardware scheduler and modification of thread manager to support the migration (of thread scheduler into the hardware). The scheduler is designed as an Intellectual Property (IP) core that can be instantiated like any peripheral core. The work is intended to enable multithreading on XILINX microkernel with a hardware thread scheduler instead of Von Neumann stored instruction scheduling execution.

Original languageEnglish
Title of host publication2008 International Conference on Electronic Design, ICED 2008
DOIs
Publication statusPublished - 01 Dec 2008
Event2008 International Conference on Electronic Design, ICED 2008 - Penang, Malaysia
Duration: 01 Dec 200803 Dec 2008

Publication series

Name2008 International Conference on Electronic Design, ICED 2008

Other

Other2008 International Conference on Electronic Design, ICED 2008
CountryMalaysia
CityPenang
Period01/12/0803/12/08

Fingerprint

Scheduling
Hardware
Field programmable gate arrays (FPGA)
Managers
Throughput

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Harmin, Y. S., Jidin, R., Moubark, A. M., & Zainol, M. A. (2008). Enabling multithreading executions on the XILINX microkernel with a hardware scheduler. In 2008 International Conference on Electronic Design, ICED 2008 [4786727] (2008 International Conference on Electronic Design, ICED 2008). https://doi.org/10.1109/ICED.2008.4786727
Harmin, Yasmin Syuhada ; Jidin, Razali ; Moubark, Asraf Mohamed ; Zainol, Mohd Amiruddin. / Enabling multithreading executions on the XILINX microkernel with a hardware scheduler. 2008 International Conference on Electronic Design, ICED 2008. 2008. (2008 International Conference on Electronic Design, ICED 2008).
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Harmin, YS, Jidin, R, Moubark, AM & Zainol, MA 2008, Enabling multithreading executions on the XILINX microkernel with a hardware scheduler. in 2008 International Conference on Electronic Design, ICED 2008., 4786727, 2008 International Conference on Electronic Design, ICED 2008, 2008 International Conference on Electronic Design, ICED 2008, Penang, Malaysia, 01/12/08. https://doi.org/10.1109/ICED.2008.4786727

Enabling multithreading executions on the XILINX microkernel with a hardware scheduler. / Harmin, Yasmin Syuhada; Jidin, Razali; Moubark, Asraf Mohamed; Zainol, Mohd Amiruddin.

2008 International Conference on Electronic Design, ICED 2008. 2008. 4786727 (2008 International Conference on Electronic Design, ICED 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Harmin YS, Jidin R, Moubark AM, Zainol MA. Enabling multithreading executions on the XILINX microkernel with a hardware scheduler. In 2008 International Conference on Electronic Design, ICED 2008. 2008. 4786727. (2008 International Conference on Electronic Design, ICED 2008). https://doi.org/10.1109/ICED.2008.4786727