Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method

A. H.Afifah Maheran, P. S. Menon, S. Shaari, T. Kalaivani, Ibrahim Ahmad, Z. A.Noor Faizah, P. R. Apte

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (Vth). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO2/Poly-Si technology. For this, Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate. The simulation results show that the optimal threshold voltage (Vth) of -0.289 V ± 12.7% is achieved in accordance to the ITRS 2012 specifications. This provides a benchmark towards the fabrication of 22 nm planar PMOS in future work.

Original languageEnglish
Title of host publicationIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages178-181
Number of pages4
ISBN (Electronic)9781479957606
DOIs
Publication statusPublished - 10 Oct 2014
Event11th IEEE International Conference on Semiconductor Electronics, ICSE 2014 - Kuala Lumpur, Malaysia
Duration: 27 Aug 201429 Aug 2014

Other

Other11th IEEE International Conference on Semiconductor Electronics, ICSE 2014
CountryMalaysia
CityKuala Lumpur
Period27/08/1429/08/14

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Maheran, A. H. A., Menon, P. S., Shaari, S., Kalaivani, T., Ahmad, I., Faizah, Z. A. N., & Apte, P. R. (2014). Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE (pp. 178-181). [6920825] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SMELEC.2014.6920825