Development of process parameters for 22 nm PMOS using 2-D analytical modeling

A. H.Afifah Maheran, P. S. Menon, Ibrahim Ahmad, S. Shaari, Z. A.Noor Faizah

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I LEAK ) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO 2 ) and tungsten silicide (WSi x ). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I LEAK where the maximum predicted I LEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/μm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in I LEAK mean value of 3.96821 nA/μm where is far lower than the predicted value.

Original languageEnglish
Title of host publicationNational Physics Conference 2014, PERFIK 2014
EditorsThian-Khok Yong, Yeong-Nan Phua, Horng-Sheng Lin, Faidz Abd Rahman
PublisherAmerican Institute of Physics Inc.
ISBN (Electronic)9780735412996
DOIs
Publication statusPublished - 24 Apr 2015
EventNational Physics Conference 2014, PERFIK 2014 - Kuala Lumpur, Malaysia
Duration: 18 Nov 201419 Nov 2014

Publication series

NameAIP Conference Proceedings
Volume1657
ISSN (Print)0094-243X
ISSN (Electronic)1551-7616

Other

OtherNational Physics Conference 2014, PERFIK 2014
CountryMalaysia
CityKuala Lumpur
Period18/11/1419/11/14

Fingerprint

transistors
CMOS
leakage
Taguchi methods
scaling
titanium oxides
implantation
tungsten
signal to noise ratios
field effect transistors
permittivity
trends
dosage
fabrication
optimization
products
metals
simulation

All Science Journal Classification (ASJC) codes

  • Physics and Astronomy(all)

Cite this

Maheran, A. H. A., Menon, P. S., Ahmad, I., Shaari, S., & Faizah, Z. A. N. (2015). Development of process parameters for 22 nm PMOS using 2-D analytical modeling. In T-K. Yong, Y-N. Phua, H-S. Lin, & F. A. Rahman (Eds.), National Physics Conference 2014, PERFIK 2014 [030007] (AIP Conference Proceedings; Vol. 1657). American Institute of Physics Inc.. https://doi.org/10.1063/1.4915157
Maheran, A. H.Afifah ; Menon, P. S. ; Ahmad, Ibrahim ; Shaari, S. ; Faizah, Z. A.Noor. / Development of process parameters for 22 nm PMOS using 2-D analytical modeling. National Physics Conference 2014, PERFIK 2014. editor / Thian-Khok Yong ; Yeong-Nan Phua ; Horng-Sheng Lin ; Faidz Abd Rahman. American Institute of Physics Inc., 2015. (AIP Conference Proceedings).
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abstract = "The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I LEAK ) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO 2 ) and tungsten silicide (WSi x ). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I LEAK where the maximum predicted I LEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/μm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49{\%} contribution in lowering the device's leakage current. The absolute process parameters combination results in I LEAK mean value of 3.96821 nA/μm where is far lower than the predicted value.",
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Maheran, AHA, Menon, PS, Ahmad, I, Shaari, S & Faizah, ZAN 2015, Development of process parameters for 22 nm PMOS using 2-D analytical modeling. in T-K Yong, Y-N Phua, H-S Lin & FA Rahman (eds), National Physics Conference 2014, PERFIK 2014., 030007, AIP Conference Proceedings, vol. 1657, American Institute of Physics Inc., National Physics Conference 2014, PERFIK 2014, Kuala Lumpur, Malaysia, 18/11/14. https://doi.org/10.1063/1.4915157

Development of process parameters for 22 nm PMOS using 2-D analytical modeling. / Maheran, A. H.Afifah; Menon, P. S.; Ahmad, Ibrahim; Shaari, S.; Faizah, Z. A.Noor.

National Physics Conference 2014, PERFIK 2014. ed. / Thian-Khok Yong; Yeong-Nan Phua; Horng-Sheng Lin; Faidz Abd Rahman. American Institute of Physics Inc., 2015. 030007 (AIP Conference Proceedings; Vol. 1657).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Maheran, A. H.Afifah

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AU - Ahmad, Ibrahim

AU - Shaari, S.

AU - Faizah, Z. A.Noor

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N2 - The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I LEAK ) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO 2 ) and tungsten silicide (WSi x ). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I LEAK where the maximum predicted I LEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/μm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in I LEAK mean value of 3.96821 nA/μm where is far lower than the predicted value.

AB - The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I LEAK ) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO 2 ) and tungsten silicide (WSi x ). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I LEAK where the maximum predicted I LEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/μm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in I LEAK mean value of 3.96821 nA/μm where is far lower than the predicted value.

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Maheran AHA, Menon PS, Ahmad I, Shaari S, Faizah ZAN. Development of process parameters for 22 nm PMOS using 2-D analytical modeling. In Yong T-K, Phua Y-N, Lin H-S, Rahman FA, editors, National Physics Conference 2014, PERFIK 2014. American Institute of Physics Inc. 2015. 030007. (AIP Conference Proceedings). https://doi.org/10.1063/1.4915157