Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA

Haider Ismael Shahadi, Razali Jidin, Wong Hung Way

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

Recently, audio steganography has become an important covert communications technology. This technology hides secret data in a cover audio without perceptual modification of the cover audio. Most of the existing audio steganography techniques are unsuitable for real-time communication. Although field programmable logic array (FPGA) technologies offer parallel processing in hardware that can improve the speed of steganographic systems, the research activities in this area are very limited. This paper presents a parallel hardware-architecture for dual-mode audio steganography (DMAS) based FPGA technology. The proposed DMAS reconfigures the same hardware blocks in both hiding and recovery modes to reduce the hardware requirements. It has been successfully implemented on a Xilinx XC6SLX16 FPGA board to occupy only 97 slices. Furthermore, it processes data simultaneously at an operating frequency of up to 58.82 MHz and accomplishes full message retrieval at an embedding rate of 25% with an audio quality above 45 dB in terms of signal to noise ratio.

Original languageEnglish
Pages (from-to)95-116
Number of pages22
JournalComputers and Electrical Engineering
Volume49
DOIs
Publication statusPublished - Jan 2016

Fingerprint

Steganography
Hardware
Communication
Signal to noise ratio
Recovery
Processing

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Computer Science(all)
  • Electrical and Electronic Engineering

Cite this

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Concurrent hardware architecture for dual-mode audio steganography processor-based FPGA. / Shahadi, Haider Ismael; Jidin, Razali; Way, Wong Hung.

In: Computers and Electrical Engineering, Vol. 49, 01.2016, p. 95-116.

Research output: Contribution to journalArticle

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