Comparative high-K material gate spacer impact in DG-finfet parameter variations between two structures

Ameer F. Roslan, F. Salehuddin, A. S.M. Zain, K. E. Kaharudin, Ibrahim Ahmad, H. Hazura, A. R. Hanim, S. K. Idris

Research output: Contribution to journalArticle

Abstract

This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs) for the 16 nm double-gate FinFET (DG-FinFET), where depletion-layer widths of the source-drain corresponds to the channel length. Virtual fabrication process along with design modification throughout the study and its electrical characterization is implemented and significant improvement is shown towards the altered structure design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio), all three materials tested being S3N4, HfO2 and TiO2 increases from the respective 60.90, 80.70 and 84.77 to 84.77, 91.54 and 92.69. That being said, the incremental in ratio has satisfied the incremental on the drive current as well as decreases the leakage current. Threshold voltage (VTH) for all dielectric materials have also satisfy the minimum requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.461±12.7% V. Based on the results obtained, the high-K materials have shown a significant improvement, specifically after the modifications towards the Source/Drain. Compared to the initial design made, TiO2 has improved by 12.94% after the alteration made in terms of the overall ION and IOFF performances through the ION/IOFF ratio value obtained, as well as meeting the required value for VTH obtained at 0.464V. The ION from high-K materials has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.

Original languageEnglish
Pages (from-to)573-580
Number of pages8
JournalIndonesian Journal of Electrical Engineering and Computer Science
Volume14
Issue number2
DOIs
Publication statusPublished - 01 May 2019

Fingerprint

Leakage Current
Leakage currents
TiO2
Semiconductor materials
Semiconductors
Threshold voltage
Requirements
Depletion
Fabrication
Voltage
Decrease
Design
FinFET

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Information Systems
  • Hardware and Architecture
  • Computer Networks and Communications
  • Control and Optimization
  • Electrical and Electronic Engineering

Cite this

Roslan, Ameer F. ; Salehuddin, F. ; Zain, A. S.M. ; Kaharudin, K. E. ; Ahmad, Ibrahim ; Hazura, H. ; Hanim, A. R. ; Idris, S. K. / Comparative high-K material gate spacer impact in DG-finfet parameter variations between two structures. In: Indonesian Journal of Electrical Engineering and Computer Science. 2019 ; Vol. 14, No. 2. pp. 573-580.
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Comparative high-K material gate spacer impact in DG-finfet parameter variations between two structures. / Roslan, Ameer F.; Salehuddin, F.; Zain, A. S.M.; Kaharudin, K. E.; Ahmad, Ibrahim; Hazura, H.; Hanim, A. R.; Idris, S. K.

In: Indonesian Journal of Electrical Engineering and Computer Science, Vol. 14, No. 2, 01.05.2019, p. 573-580.

Research output: Contribution to journalArticle

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T1 - Comparative high-K material gate spacer impact in DG-finfet parameter variations between two structures

AU - Roslan, Ameer F.

AU - Salehuddin, F.

AU - Zain, A. S.M.

AU - Kaharudin, K. E.

AU - Ahmad, Ibrahim

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AU - Hanim, A. R.

AU - Idris, S. K.

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AB - This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs) for the 16 nm double-gate FinFET (DG-FinFET), where depletion-layer widths of the source-drain corresponds to the channel length. Virtual fabrication process along with design modification throughout the study and its electrical characterization is implemented and significant improvement is shown towards the altered structure design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio), all three materials tested being S3N4, HfO2 and TiO2 increases from the respective 60.90, 80.70 and 84.77 to 84.77, 91.54 and 92.69. That being said, the incremental in ratio has satisfied the incremental on the drive current as well as decreases the leakage current. Threshold voltage (VTH) for all dielectric materials have also satisfy the minimum requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.461±12.7% V. Based on the results obtained, the high-K materials have shown a significant improvement, specifically after the modifications towards the Source/Drain. Compared to the initial design made, TiO2 has improved by 12.94% after the alteration made in terms of the overall ION and IOFF performances through the ION/IOFF ratio value obtained, as well as meeting the required value for VTH obtained at 0.464V. The ION from high-K materials has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.

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