The poly-Si/SiO2 based MOSFETs have been encountering a problem with the limitation of channel length for the device miniaturization. The drain induced barrier lowering (DIBL) effect is the main threat for the device to acquire excellent device's characteristics. Thus, the metal-gate/high-k technology is a smart choice for the future replacement of poly-Si/SiO2 channel. This paper introduces the implementation of WSix/TiO2 channel to replace the poly-Si/SiO2 channel in vertical double-gate NMOS structure, followed by the application of Taguchi method to reduce the drain induced barrier lowering (DIBL) effects. The device was virtually fabricated and characterized by using both ATHENA and ATLAS modules of SILVACO TCAD tools. The L12 orthogonal array, main effects, signal-to noise ratio (SNR) and analysis of variance (ANOVA) were utilized to analyze the effect of process parameter variations on the DIBL. Later, the interactions between the process parameters were investigated by using L8 orthogonal array of Taguchi method. Based on the final results, halo implant tilt angle and source/drain (S/D) implant energy were identified as the most dominant process parameters where each of them contributes 24% and 16% of factor effects on SNR respectively. The lowest possible value of DIBL after the optimization with the interaction test is 1.552 mV/V.
|Number of pages||11|
|Journal||ARPN Journal of Engineering and Applied Sciences|
|Publication status||Published - Jun 2016|
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