Application of Taguchi method in the optimization of process variation for 32nm CMOS technology

H. A. Elgomati, B. Y. Majlis, Ibrahim Ahmad, F. Salehuddin, Fazrena Azlee Hamid, A. Zaharim, P. R. Apte

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determined by Taguchi method in experimental design. The influence of the main process parameters on threshold voltage were determined using analysis of variance (ANOVA). The fabrication processes of the transistor were performed by a simulator namely ATHENA. The electrical characterization of the device was done by the a simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing process parameters. The other two parameter used in this experiments were Source/Drain (S/D) implantation dose and, silicide annealing temperature Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of 0.10308V and -0.10319V for NMOS and PMOS respectively. As conclusion, by utilizing Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.103V that is well within ITRS prediction for 32nm transistor.

Original languageEnglish
Pages (from-to)346-355
Number of pages10
JournalAustralian Journal of Basic and Applied Sciences
Volume5
Issue number7
Publication statusPublished - 01 Jul 2011

Fingerprint

Taguchi methods
Threshold voltage
Simulators
Metals
Transistors
Annealing
Analysis of variance (ANOVA)
Design of experiments
Fabrication
Oxide semiconductors
Experiments
Temperature

All Science Journal Classification (ASJC) codes

  • General

Cite this

@article{c5bbc9d2161743f38eb1d6c6f8d27f7c,
title = "Application of Taguchi method in the optimization of process variation for 32nm CMOS technology",
abstract = "In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determined by Taguchi method in experimental design. The influence of the main process parameters on threshold voltage were determined using analysis of variance (ANOVA). The fabrication processes of the transistor were performed by a simulator namely ATHENA. The electrical characterization of the device was done by the a simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing process parameters. The other two parameter used in this experiments were Source/Drain (S/D) implantation dose and, silicide annealing temperature Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of 0.10308V and -0.10319V for NMOS and PMOS respectively. As conclusion, by utilizing Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.103V that is well within ITRS prediction for 32nm transistor.",
author = "Elgomati, {H. A.} and Majlis, {B. Y.} and Ibrahim Ahmad and F. Salehuddin and Hamid, {Fazrena Azlee} and A. Zaharim and Apte, {P. R.}",
year = "2011",
month = "7",
day = "1",
language = "English",
volume = "5",
pages = "346--355",
journal = "Australian Journal of Basic and Applied Sciences",
issn = "1991-8178",
publisher = "INSInet Publications",
number = "7",

}

Application of Taguchi method in the optimization of process variation for 32nm CMOS technology. / Elgomati, H. A.; Majlis, B. Y.; Ahmad, Ibrahim; Salehuddin, F.; Hamid, Fazrena Azlee; Zaharim, A.; Apte, P. R.

In: Australian Journal of Basic and Applied Sciences, Vol. 5, No. 7, 01.07.2011, p. 346-355.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Application of Taguchi method in the optimization of process variation for 32nm CMOS technology

AU - Elgomati, H. A.

AU - Majlis, B. Y.

AU - Ahmad, Ibrahim

AU - Salehuddin, F.

AU - Hamid, Fazrena Azlee

AU - Zaharim, A.

AU - Apte, P. R.

PY - 2011/7/1

Y1 - 2011/7/1

N2 - In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determined by Taguchi method in experimental design. The influence of the main process parameters on threshold voltage were determined using analysis of variance (ANOVA). The fabrication processes of the transistor were performed by a simulator namely ATHENA. The electrical characterization of the device was done by the a simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing process parameters. The other two parameter used in this experiments were Source/Drain (S/D) implantation dose and, silicide annealing temperature Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of 0.10308V and -0.10319V for NMOS and PMOS respectively. As conclusion, by utilizing Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.103V that is well within ITRS prediction for 32nm transistor.

AB - In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determined by Taguchi method in experimental design. The influence of the main process parameters on threshold voltage were determined using analysis of variance (ANOVA). The fabrication processes of the transistor were performed by a simulator namely ATHENA. The electrical characterization of the device was done by the a simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing process parameters. The other two parameter used in this experiments were Source/Drain (S/D) implantation dose and, silicide annealing temperature Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of 0.10308V and -0.10319V for NMOS and PMOS respectively. As conclusion, by utilizing Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.103V that is well within ITRS prediction for 32nm transistor.

UR - http://www.scopus.com/inward/record.url?scp=79960517117&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79960517117&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:79960517117

VL - 5

SP - 346

EP - 355

JO - Australian Journal of Basic and Applied Sciences

JF - Australian Journal of Basic and Applied Sciences

SN - 1991-8178

IS - 7

ER -