Application of Taguchi method in designing a 22nm high-k/metal gate NMOS transistor

A. H. Afifah Maheran, P. S. Menon, Ibrahim Ahmad, S. Shaari

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper reports on the application of Taguchi method in modelling a 22nm gate length high-k/metal gate NMOS transistor. The Nominal-the-Best Signal-to-noise Ratio (SNR) using Taguchi's optimization technique was utilized to optimize the process parameters in determining the best threshold voltage (Vth) value where it was used as the evaluation variable. The high permittivity material (high-k) / metal gate device consists of titanium dioxide (TiO2) and tungsten silicide (WSix) respectively. The simulation work was executed using a TCAD simulator, which consist of ATHENA and ATLAS as a process and device simulator respectively. In this research, the Halo implantation tilting angle was identified as the most influencial factor in affecting the Vth with a percentage of 87%, followed by the oxide growth anneal temperature (8%), the metal gate anneal temperature (4%) and lastly the Halo implantation dose (1%). As a conclusion, the Halo tilting angle is the dominant factor in optimizing the process parameter. Meanwhile the Halo implantation dose can be considered as an adjustment factor in order to achieve the target Vth value of 0.289 V which is in line with projections made by the International Technology Roadmap for Semiconductors (ITRS).

Original languageEnglish
Title of host publicationMicro/Nano Science and Engineering
PublisherTrans Tech Publications
Pages514-518
Number of pages5
ISBN (Print)9783038350866
DOIs
Publication statusPublished - 01 Jan 2014
EventJoint International Conference on Nanoscience, Engineering and Management, BOND21 - Penang, Malaysia
Duration: 19 Aug 201321 Aug 2013

Publication series

NameAdvanced Materials Research
Volume925
ISSN (Print)1022-6680

Other

OtherJoint International Conference on Nanoscience, Engineering and Management, BOND21
CountryMalaysia
CityPenang
Period19/08/1321/08/13

Fingerprint

Taguchi methods
Transistors
Simulators
Metals
Growth temperature
Threshold voltage
Titanium dioxide
Tungsten
Signal to noise ratio
Permittivity
Semiconductor materials
Oxides
Temperature

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Afifah Maheran, A. H., Menon, P. S., Ahmad, I., & Shaari, S. (2014). Application of Taguchi method in designing a 22nm high-k/metal gate NMOS transistor. In Micro/Nano Science and Engineering (pp. 514-518). (Advanced Materials Research; Vol. 925). Trans Tech Publications. https://doi.org/10.4028/www.scientific.net/AMR.925.514
Afifah Maheran, A. H. ; Menon, P. S. ; Ahmad, Ibrahim ; Shaari, S. / Application of Taguchi method in designing a 22nm high-k/metal gate NMOS transistor. Micro/Nano Science and Engineering. Trans Tech Publications, 2014. pp. 514-518 (Advanced Materials Research).
@inproceedings{81f5293f4e6249cdb18876c69eff54ba,
title = "Application of Taguchi method in designing a 22nm high-k/metal gate NMOS transistor",
abstract = "This paper reports on the application of Taguchi method in modelling a 22nm gate length high-k/metal gate NMOS transistor. The Nominal-the-Best Signal-to-noise Ratio (SNR) using Taguchi's optimization technique was utilized to optimize the process parameters in determining the best threshold voltage (Vth) value where it was used as the evaluation variable. The high permittivity material (high-k) / metal gate device consists of titanium dioxide (TiO2) and tungsten silicide (WSix) respectively. The simulation work was executed using a TCAD simulator, which consist of ATHENA and ATLAS as a process and device simulator respectively. In this research, the Halo implantation tilting angle was identified as the most influencial factor in affecting the Vth with a percentage of 87{\%}, followed by the oxide growth anneal temperature (8{\%}), the metal gate anneal temperature (4{\%}) and lastly the Halo implantation dose (1{\%}). As a conclusion, the Halo tilting angle is the dominant factor in optimizing the process parameter. Meanwhile the Halo implantation dose can be considered as an adjustment factor in order to achieve the target Vth value of 0.289 V which is in line with projections made by the International Technology Roadmap for Semiconductors (ITRS).",
author = "{Afifah Maheran}, {A. H.} and Menon, {P. S.} and Ibrahim Ahmad and S. Shaari",
year = "2014",
month = "1",
day = "1",
doi = "10.4028/www.scientific.net/AMR.925.514",
language = "English",
isbn = "9783038350866",
series = "Advanced Materials Research",
publisher = "Trans Tech Publications",
pages = "514--518",
booktitle = "Micro/Nano Science and Engineering",
address = "Germany",

}

Afifah Maheran, AH, Menon, PS, Ahmad, I & Shaari, S 2014, Application of Taguchi method in designing a 22nm high-k/metal gate NMOS transistor. in Micro/Nano Science and Engineering. Advanced Materials Research, vol. 925, Trans Tech Publications, pp. 514-518, Joint International Conference on Nanoscience, Engineering and Management, BOND21, Penang, Malaysia, 19/08/13. https://doi.org/10.4028/www.scientific.net/AMR.925.514

Application of Taguchi method in designing a 22nm high-k/metal gate NMOS transistor. / Afifah Maheran, A. H.; Menon, P. S.; Ahmad, Ibrahim; Shaari, S.

Micro/Nano Science and Engineering. Trans Tech Publications, 2014. p. 514-518 (Advanced Materials Research; Vol. 925).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Application of Taguchi method in designing a 22nm high-k/metal gate NMOS transistor

AU - Afifah Maheran, A. H.

AU - Menon, P. S.

AU - Ahmad, Ibrahim

AU - Shaari, S.

PY - 2014/1/1

Y1 - 2014/1/1

N2 - This paper reports on the application of Taguchi method in modelling a 22nm gate length high-k/metal gate NMOS transistor. The Nominal-the-Best Signal-to-noise Ratio (SNR) using Taguchi's optimization technique was utilized to optimize the process parameters in determining the best threshold voltage (Vth) value where it was used as the evaluation variable. The high permittivity material (high-k) / metal gate device consists of titanium dioxide (TiO2) and tungsten silicide (WSix) respectively. The simulation work was executed using a TCAD simulator, which consist of ATHENA and ATLAS as a process and device simulator respectively. In this research, the Halo implantation tilting angle was identified as the most influencial factor in affecting the Vth with a percentage of 87%, followed by the oxide growth anneal temperature (8%), the metal gate anneal temperature (4%) and lastly the Halo implantation dose (1%). As a conclusion, the Halo tilting angle is the dominant factor in optimizing the process parameter. Meanwhile the Halo implantation dose can be considered as an adjustment factor in order to achieve the target Vth value of 0.289 V which is in line with projections made by the International Technology Roadmap for Semiconductors (ITRS).

AB - This paper reports on the application of Taguchi method in modelling a 22nm gate length high-k/metal gate NMOS transistor. The Nominal-the-Best Signal-to-noise Ratio (SNR) using Taguchi's optimization technique was utilized to optimize the process parameters in determining the best threshold voltage (Vth) value where it was used as the evaluation variable. The high permittivity material (high-k) / metal gate device consists of titanium dioxide (TiO2) and tungsten silicide (WSix) respectively. The simulation work was executed using a TCAD simulator, which consist of ATHENA and ATLAS as a process and device simulator respectively. In this research, the Halo implantation tilting angle was identified as the most influencial factor in affecting the Vth with a percentage of 87%, followed by the oxide growth anneal temperature (8%), the metal gate anneal temperature (4%) and lastly the Halo implantation dose (1%). As a conclusion, the Halo tilting angle is the dominant factor in optimizing the process parameter. Meanwhile the Halo implantation dose can be considered as an adjustment factor in order to achieve the target Vth value of 0.289 V which is in line with projections made by the International Technology Roadmap for Semiconductors (ITRS).

UR - http://www.scopus.com/inward/record.url?scp=84901702197&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84901702197&partnerID=8YFLogxK

U2 - 10.4028/www.scientific.net/AMR.925.514

DO - 10.4028/www.scientific.net/AMR.925.514

M3 - Conference contribution

SN - 9783038350866

T3 - Advanced Materials Research

SP - 514

EP - 518

BT - Micro/Nano Science and Engineering

PB - Trans Tech Publications

ER -

Afifah Maheran AH, Menon PS, Ahmad I, Shaari S. Application of Taguchi method in designing a 22nm high-k/metal gate NMOS transistor. In Micro/Nano Science and Engineering. Trans Tech Publications. 2014. p. 514-518. (Advanced Materials Research). https://doi.org/10.4028/www.scientific.net/AMR.925.514