Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method

Fauziyah Salehuddin, Ibrahim Ahmad, Fazrena Azlee Hamid, Azami Zaharim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Taguchi method was used to analyze the experimental data in order to get the optimum average of silicide thickness in 45nm devices. The virtually fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were used as design tools and helps to reduce design time and cost. In this paper, both modules and Taguchi method was combined to aid in design and optimizer the process parameters. There are four process parameters (factors), namely Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. These factors were varied for 3 levels to perform 9 experiments. Threshold voltage (VTH) results were used as the evaluation variables. Then, the results were subjected to the Taguchi method for determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were successfully verified with ATHENA and ATLAS's simulator. The results show that the average of silicide thickness after optimizations approaches was 30.66nm and 30.58nm for NMOS and PMOS devices respectively. In this research, Halo Implantation was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as an adjustment factor to get the nominal values of threshold voltage for PMOS and NMOS devices equal to -0.1501V and +0.150047V respectively.

Original languageEnglish
Title of host publicationICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics
Pages19-24
Number of pages6
DOIs
Publication statusPublished - 11 Oct 2010
Event2010 IEEE International Conference on Semiconductor Electronics, ICSE 2010 - Melaka, Malaysia
Duration: 28 Jun 201030 Jun 2010

Other

Other2010 IEEE International Conference on Semiconductor Electronics, ICSE 2010
CountryMalaysia
CityMelaka
Period28/06/1030/06/10

Fingerprint

Taguchi methods
Threshold voltage
Growth temperature
Oxides
Simulators
Fabrication
Costs
Experiments
Temperature

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Salehuddin, F., Ahmad, I., Hamid, F. A., & Zaharim, A. (2010). Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method. In ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics (pp. 19-24). [5549488] https://doi.org/10.1109/SMELEC.2010.5549488
Salehuddin, Fauziyah ; Ahmad, Ibrahim ; Hamid, Fazrena Azlee ; Zaharim, Azami. / Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method. ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics. 2010. pp. 19-24
@inproceedings{d90e34a4863c43cc86d8a7be577c81f8,
title = "Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method",
abstract = "Taguchi method was used to analyze the experimental data in order to get the optimum average of silicide thickness in 45nm devices. The virtually fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were used as design tools and helps to reduce design time and cost. In this paper, both modules and Taguchi method was combined to aid in design and optimizer the process parameters. There are four process parameters (factors), namely Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. These factors were varied for 3 levels to perform 9 experiments. Threshold voltage (VTH) results were used as the evaluation variables. Then, the results were subjected to the Taguchi method for determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were successfully verified with ATHENA and ATLAS's simulator. The results show that the average of silicide thickness after optimizations approaches was 30.66nm and 30.58nm for NMOS and PMOS devices respectively. In this research, Halo Implantation was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as an adjustment factor to get the nominal values of threshold voltage for PMOS and NMOS devices equal to -0.1501V and +0.150047V respectively.",
author = "Fauziyah Salehuddin and Ibrahim Ahmad and Hamid, {Fazrena Azlee} and Azami Zaharim",
year = "2010",
month = "10",
day = "11",
doi = "10.1109/SMELEC.2010.5549488",
language = "English",
isbn = "9781424466092",
pages = "19--24",
booktitle = "ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics",

}

Salehuddin, F, Ahmad, I, Hamid, FA & Zaharim, A 2010, Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method. in ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics., 5549488, pp. 19-24, 2010 IEEE International Conference on Semiconductor Electronics, ICSE 2010, Melaka, Malaysia, 28/06/10. https://doi.org/10.1109/SMELEC.2010.5549488

Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method. / Salehuddin, Fauziyah; Ahmad, Ibrahim; Hamid, Fazrena Azlee; Zaharim, Azami.

ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics. 2010. p. 19-24 5549488.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method

AU - Salehuddin, Fauziyah

AU - Ahmad, Ibrahim

AU - Hamid, Fazrena Azlee

AU - Zaharim, Azami

PY - 2010/10/11

Y1 - 2010/10/11

N2 - Taguchi method was used to analyze the experimental data in order to get the optimum average of silicide thickness in 45nm devices. The virtually fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were used as design tools and helps to reduce design time and cost. In this paper, both modules and Taguchi method was combined to aid in design and optimizer the process parameters. There are four process parameters (factors), namely Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. These factors were varied for 3 levels to perform 9 experiments. Threshold voltage (VTH) results were used as the evaluation variables. Then, the results were subjected to the Taguchi method for determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were successfully verified with ATHENA and ATLAS's simulator. The results show that the average of silicide thickness after optimizations approaches was 30.66nm and 30.58nm for NMOS and PMOS devices respectively. In this research, Halo Implantation was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as an adjustment factor to get the nominal values of threshold voltage for PMOS and NMOS devices equal to -0.1501V and +0.150047V respectively.

AB - Taguchi method was used to analyze the experimental data in order to get the optimum average of silicide thickness in 45nm devices. The virtually fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were used as design tools and helps to reduce design time and cost. In this paper, both modules and Taguchi method was combined to aid in design and optimizer the process parameters. There are four process parameters (factors), namely Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. These factors were varied for 3 levels to perform 9 experiments. Threshold voltage (VTH) results were used as the evaluation variables. Then, the results were subjected to the Taguchi method for determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were successfully verified with ATHENA and ATLAS's simulator. The results show that the average of silicide thickness after optimizations approaches was 30.66nm and 30.58nm for NMOS and PMOS devices respectively. In this research, Halo Implantation was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as an adjustment factor to get the nominal values of threshold voltage for PMOS and NMOS devices equal to -0.1501V and +0.150047V respectively.

UR - http://www.scopus.com/inward/record.url?scp=77957565255&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77957565255&partnerID=8YFLogxK

U2 - 10.1109/SMELEC.2010.5549488

DO - 10.1109/SMELEC.2010.5549488

M3 - Conference contribution

SN - 9781424466092

SP - 19

EP - 24

BT - ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics

ER -

Salehuddin F, Ahmad I, Hamid FA, Zaharim A. Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method. In ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics. 2010. p. 19-24. 5549488 https://doi.org/10.1109/SMELEC.2010.5549488