Analysis the effect of control factors optimization on the threshold voltage of 18 nm PMOS using L27 taguchi method

Norani Bte Atanb, Burhanuddin Yeop Majlis, Ibrahim Ahmad, Kok Hen Chong

Research output: Contribution to journalArticle

Abstract

This research paper is about the investigation of Halo Implantation, Halo Implantation Energy, Halo Tilt, Compensation Implantation and Source/Drain Implantation. They are types of control factors that used in achievement of the threshold voltage value. To support the successfully of the threshold voltage (VTH) producing, Taguchi method by using L27 orthogonal array was used to optimize the control factors variation. This analysis has involved with 2 main factors which are break down into five control factors and two noise factors. The five control factors were varied with three levels of each and the two noise factors were varied with two levels of each in 27 experiments. In Taguchi method, the statistics data of 18 nm PMOS transistor are from the signal noise ratio (SNR) with nominal-the best (NTB) and the analysis of variance (ANOVA) are executed to minimize the variance of threshold voltage. This experiment implanted by using Virtual Wafer Fabrication SILVACO software which is to design and fabricate the transistor device. Experimental results revealed that the optimization method is achieved to perform the threshold voltage value with least variance and the percent, which is only 2.16%. The threshold voltage value from the experiment shows -0.308517 volts while the target value that is -0.302 volts from value of International Technology Roadmap of semiconductor, ITRS 2012. The threshold voltage value for 18 nm PMOS transistor is well within the range of -0.302 ± 12.7% volts that is recommendation by the International Roadmap for Semiconductor prediction 2012.

Original languageEnglish
Pages (from-to)934-942
Number of pages9
JournalIndonesian Journal of Electrical Engineering and Computer Science
Volume10
Issue number3
DOIs
Publication statusPublished - 01 Jun 2018

Fingerprint

Taguchi Method
Taguchi methods
Threshold voltage
Implantation
Voltage
Optimization
Noise Factor
Transistors
Semiconductors
Semiconductor materials
Experiment
Orthogonal Array
Experiments
Analysis of variance
Tilt
Analysis of variance (ANOVA)
Wafer
Percent
Categorical or nominal
Breakdown

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Information Systems
  • Hardware and Architecture
  • Computer Networks and Communications
  • Control and Optimization
  • Electrical and Electronic Engineering

Cite this

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title = "Analysis the effect of control factors optimization on the threshold voltage of 18 nm PMOS using L27 taguchi method",
abstract = "This research paper is about the investigation of Halo Implantation, Halo Implantation Energy, Halo Tilt, Compensation Implantation and Source/Drain Implantation. They are types of control factors that used in achievement of the threshold voltage value. To support the successfully of the threshold voltage (VTH) producing, Taguchi method by using L27 orthogonal array was used to optimize the control factors variation. This analysis has involved with 2 main factors which are break down into five control factors and two noise factors. The five control factors were varied with three levels of each and the two noise factors were varied with two levels of each in 27 experiments. In Taguchi method, the statistics data of 18 nm PMOS transistor are from the signal noise ratio (SNR) with nominal-the best (NTB) and the analysis of variance (ANOVA) are executed to minimize the variance of threshold voltage. This experiment implanted by using Virtual Wafer Fabrication SILVACO software which is to design and fabricate the transistor device. Experimental results revealed that the optimization method is achieved to perform the threshold voltage value with least variance and the percent, which is only 2.16{\%}. The threshold voltage value from the experiment shows -0.308517 volts while the target value that is -0.302 volts from value of International Technology Roadmap of semiconductor, ITRS 2012. The threshold voltage value for 18 nm PMOS transistor is well within the range of -0.302 ± 12.7{\%} volts that is recommendation by the International Roadmap for Semiconductor prediction 2012.",
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Analysis the effect of control factors optimization on the threshold voltage of 18 nm PMOS using L27 taguchi method. / Bte Atanb, Norani; Majlis, Burhanuddin Yeop; Ahmad, Ibrahim; Chong, Kok Hen.

In: Indonesian Journal of Electrical Engineering and Computer Science, Vol. 10, No. 3, 01.06.2018, p. 934-942.

Research output: Contribution to journalArticle

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