A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility

Mohd Azizi Chik, Ve Chun Yung, Puvaneswaran Balakrishna, Uda Hashim, Ibrahim Ahmad, Bashir Mohamad

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

This research is to study the opportunity to achieve optimum productivity yield in 0.16μm product mixed through understanding the impact of loading utilization towards the capacity. The study is important to model the overall strategy of product loading planning to get highest achievable product output at respective time like monthly or yearly. The product mixes target used in this analysis includes 0.20um to 0.13um for high voltage, logic CMOS and also mixed signal RF. Input in analysis are list of process flow for various technologies and products, major manufacturing activities and equipment configuration that is based on actual wafer fabrication facilities systems. Part of the complexities of the research is its long cycle time process from 45minutes to 9 hours, for respective same processing step that drives from varies technology and process equipment capable. Overall cycle time is from 30 days to 90 days that is various comparing product-to-product requirements. Further added to the complexity is the equipment used for this analysis that is more than 100 difference equipment configurations. More than 50% of the equipments are with difference configuration. Most products experienced re-entranced more than 85% times to same equipment type. This analysis done on generic semiconductor fab modeled using industries software, AutoSchedAP. The fab model configured intensively so match with exactly operation of the fab, with equivalent almost 100% manufacturing operation, product loading and tool configuration. The results have been successfully developed into a curve an equation shows the optimum product loading and gives opportunity of improvement in revenue and also overall efficiency of more than 10%. Further results of this study also summarized ranges of fab utilization versus cycle time that support overall product delivery. Other impacts are also discussed in the summary.

Original languageEnglish
Title of host publicationICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics
Pages377-380
Number of pages4
DOIs
Publication statusPublished - 11 Oct 2010
Event2010 IEEE International Conference on Semiconductor Electronics, ICSE 2010 - Melaka, Malaysia
Duration: 28 Jun 201030 Jun 2010

Other

Other2010 IEEE International Conference on Semiconductor Electronics, ICSE 2010
CountryMalaysia
CityMelaka
Period28/06/1030/06/10

Fingerprint

Productivity
Fabrication
Semiconductor materials
Planning
Electric potential
Processing
Industry

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Chik, M. A., Yung, V. C., Balakrishna, P., Hashim, U., Ahmad, I., & Mohamad, B. (2010). A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility. In ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics (pp. 377-380). [5549356] https://doi.org/10.1109/SMELEC.2010.5549356
Chik, Mohd Azizi ; Yung, Ve Chun ; Balakrishna, Puvaneswaran ; Hashim, Uda ; Ahmad, Ibrahim ; Mohamad, Bashir. / A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility. ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics. 2010. pp. 377-380
@inproceedings{9ad552855c7348598a221474b7a0f532,
title = "A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility",
abstract = "This research is to study the opportunity to achieve optimum productivity yield in 0.16μm product mixed through understanding the impact of loading utilization towards the capacity. The study is important to model the overall strategy of product loading planning to get highest achievable product output at respective time like monthly or yearly. The product mixes target used in this analysis includes 0.20um to 0.13um for high voltage, logic CMOS and also mixed signal RF. Input in analysis are list of process flow for various technologies and products, major manufacturing activities and equipment configuration that is based on actual wafer fabrication facilities systems. Part of the complexities of the research is its long cycle time process from 45minutes to 9 hours, for respective same processing step that drives from varies technology and process equipment capable. Overall cycle time is from 30 days to 90 days that is various comparing product-to-product requirements. Further added to the complexity is the equipment used for this analysis that is more than 100 difference equipment configurations. More than 50{\%} of the equipments are with difference configuration. Most products experienced re-entranced more than 85{\%} times to same equipment type. This analysis done on generic semiconductor fab modeled using industries software, AutoSchedAP. The fab model configured intensively so match with exactly operation of the fab, with equivalent almost 100{\%} manufacturing operation, product loading and tool configuration. The results have been successfully developed into a curve an equation shows the optimum product loading and gives opportunity of improvement in revenue and also overall efficiency of more than 10{\%}. Further results of this study also summarized ranges of fab utilization versus cycle time that support overall product delivery. Other impacts are also discussed in the summary.",
author = "Chik, {Mohd Azizi} and Yung, {Ve Chun} and Puvaneswaran Balakrishna and Uda Hashim and Ibrahim Ahmad and Bashir Mohamad",
year = "2010",
month = "10",
day = "11",
doi = "10.1109/SMELEC.2010.5549356",
language = "English",
isbn = "9781424466092",
pages = "377--380",
booktitle = "ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics",

}

Chik, MA, Yung, VC, Balakrishna, P, Hashim, U, Ahmad, I & Mohamad, B 2010, A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility. in ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics., 5549356, pp. 377-380, 2010 IEEE International Conference on Semiconductor Electronics, ICSE 2010, Melaka, Malaysia, 28/06/10. https://doi.org/10.1109/SMELEC.2010.5549356

A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility. / Chik, Mohd Azizi; Yung, Ve Chun; Balakrishna, Puvaneswaran; Hashim, Uda; Ahmad, Ibrahim; Mohamad, Bashir.

ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics. 2010. p. 377-380 5549356.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility

AU - Chik, Mohd Azizi

AU - Yung, Ve Chun

AU - Balakrishna, Puvaneswaran

AU - Hashim, Uda

AU - Ahmad, Ibrahim

AU - Mohamad, Bashir

PY - 2010/10/11

Y1 - 2010/10/11

N2 - This research is to study the opportunity to achieve optimum productivity yield in 0.16μm product mixed through understanding the impact of loading utilization towards the capacity. The study is important to model the overall strategy of product loading planning to get highest achievable product output at respective time like monthly or yearly. The product mixes target used in this analysis includes 0.20um to 0.13um for high voltage, logic CMOS and also mixed signal RF. Input in analysis are list of process flow for various technologies and products, major manufacturing activities and equipment configuration that is based on actual wafer fabrication facilities systems. Part of the complexities of the research is its long cycle time process from 45minutes to 9 hours, for respective same processing step that drives from varies technology and process equipment capable. Overall cycle time is from 30 days to 90 days that is various comparing product-to-product requirements. Further added to the complexity is the equipment used for this analysis that is more than 100 difference equipment configurations. More than 50% of the equipments are with difference configuration. Most products experienced re-entranced more than 85% times to same equipment type. This analysis done on generic semiconductor fab modeled using industries software, AutoSchedAP. The fab model configured intensively so match with exactly operation of the fab, with equivalent almost 100% manufacturing operation, product loading and tool configuration. The results have been successfully developed into a curve an equation shows the optimum product loading and gives opportunity of improvement in revenue and also overall efficiency of more than 10%. Further results of this study also summarized ranges of fab utilization versus cycle time that support overall product delivery. Other impacts are also discussed in the summary.

AB - This research is to study the opportunity to achieve optimum productivity yield in 0.16μm product mixed through understanding the impact of loading utilization towards the capacity. The study is important to model the overall strategy of product loading planning to get highest achievable product output at respective time like monthly or yearly. The product mixes target used in this analysis includes 0.20um to 0.13um for high voltage, logic CMOS and also mixed signal RF. Input in analysis are list of process flow for various technologies and products, major manufacturing activities and equipment configuration that is based on actual wafer fabrication facilities systems. Part of the complexities of the research is its long cycle time process from 45minutes to 9 hours, for respective same processing step that drives from varies technology and process equipment capable. Overall cycle time is from 30 days to 90 days that is various comparing product-to-product requirements. Further added to the complexity is the equipment used for this analysis that is more than 100 difference equipment configurations. More than 50% of the equipments are with difference configuration. Most products experienced re-entranced more than 85% times to same equipment type. This analysis done on generic semiconductor fab modeled using industries software, AutoSchedAP. The fab model configured intensively so match with exactly operation of the fab, with equivalent almost 100% manufacturing operation, product loading and tool configuration. The results have been successfully developed into a curve an equation shows the optimum product loading and gives opportunity of improvement in revenue and also overall efficiency of more than 10%. Further results of this study also summarized ranges of fab utilization versus cycle time that support overall product delivery. Other impacts are also discussed in the summary.

UR - http://www.scopus.com/inward/record.url?scp=77957555114&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77957555114&partnerID=8YFLogxK

U2 - 10.1109/SMELEC.2010.5549356

DO - 10.1109/SMELEC.2010.5549356

M3 - Conference contribution

AN - SCOPUS:77957555114

SN - 9781424466092

SP - 377

EP - 380

BT - ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics

ER -

Chik MA, Yung VC, Balakrishna P, Hashim U, Ahmad I, Mohamad B. A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility. In ICSE 2010 - Proceedings IEEE International Conference on Semiconductor Electronics. 2010. p. 377-380. 5549356 https://doi.org/10.1109/SMELEC.2010.5549356