A simulation approach for dispatching techniques comparison in 200mm wafer foundry

M. A. Chik, Ibrahim Ahmad, Md Yusoff Jamaluddin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper focuses on the comparison of the fundamental techniques for lot dispatching to reveal results for optimum product cycle time. The model is built, based on the 200mm-wafer size, 12K product Work In Progress (WIP), 10 product mixes in the current WIP with 2 new prototype product start daily, for 3K-wafer start per week (WSPW) capacity. The fundamental dispatching rules to be compared are includes First In First Out (FIFO), Shortest Processing Time (SPT), Critical Ratio (CR), Earliest due date (EDD), Shortest Remaining Processing Time (SRPT) and Random (RAN). In the comparison, a snap shot of WIP and product mix were taken at the wafer processing station from pad oxidation cleaning process to alloy. The result then is generated from the commercial simulation software, where requirements such as product cycle time, manufacturing efficiency, equipment availability, product yield and WIP profile are the inputs for the model. The results reveal that CR dispatching rule gives the shortest cycle time for a product to complete all the processes of wafer fabrication by 6% to 13% compared to the other five dispatching rules. Further analyzing for better cycle time, a combination of dispatching rule that consists of CR and SRPT has been tested and yielded 10% additional shorter cycle time compared to CR rule, which make overall improvement to maximum of 23% for overall finding. The result of these finding has been successfully accepted and realization in the real wafer fabrication operation.

Original languageEnglish
Title of host publication2004 IEEE International Conference on Semiconductor Electronics, ICSE 2004
Pages645-649
Number of pages5
Publication statusPublished - 2004
Event2004 IEEE International Conference on Semiconductor Electronics, ICSE 2004 - Kuala Lumpur, Malaysia
Duration: 04 Dec 200409 Dec 2004

Other

Other2004 IEEE International Conference on Semiconductor Electronics, ICSE 2004
CountryMalaysia
CityKuala Lumpur
Period04/12/0409/12/04

Fingerprint

Foundries
Processing
Fabrication
Cleaning
Availability
Oxidation

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Chik, M. A., Ahmad, I., & Jamaluddin, M. Y. (2004). A simulation approach for dispatching techniques comparison in 200mm wafer foundry. In 2004 IEEE International Conference on Semiconductor Electronics, ICSE 2004 (pp. 645-649). [1620969]
Chik, M. A. ; Ahmad, Ibrahim ; Jamaluddin, Md Yusoff. / A simulation approach for dispatching techniques comparison in 200mm wafer foundry. 2004 IEEE International Conference on Semiconductor Electronics, ICSE 2004. 2004. pp. 645-649
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Chik, MA, Ahmad, I & Jamaluddin, MY 2004, A simulation approach for dispatching techniques comparison in 200mm wafer foundry. in 2004 IEEE International Conference on Semiconductor Electronics, ICSE 2004., 1620969, pp. 645-649, 2004 IEEE International Conference on Semiconductor Electronics, ICSE 2004, Kuala Lumpur, Malaysia, 04/12/04.

A simulation approach for dispatching techniques comparison in 200mm wafer foundry. / Chik, M. A.; Ahmad, Ibrahim; Jamaluddin, Md Yusoff.

2004 IEEE International Conference on Semiconductor Electronics, ICSE 2004. 2004. p. 645-649 1620969.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chik MA, Ahmad I, Jamaluddin MY. A simulation approach for dispatching techniques comparison in 200mm wafer foundry. In 2004 IEEE International Conference on Semiconductor Electronics, ICSE 2004. 2004. p. 645-649. 1620969