A comparative study of Smart Card design with Memory ciphering system on Arm-Based FPGA

Wira Firdaus Yaakob, Hazleen Aris, Jahariah Sampe

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1 Citation (Scopus)

Abstract

Memory ciphering system is amechanism to secure the data in non-volatile memories of the system using standard encryption module and other security protectiom. Memory ciphering system in a smart card consists of three impodant units. Advanced Encryption Standard (AES) cipher, Random Number Generator (RNG) and ScramblerIDescrambler. It is built imide the Memory Management Processing Unit (MMPU) for securlng data transactions with the smart cardmemories Ths study presents the results of a comparative study performed between Xilinx's and Intel's (previously Altera) Advanced RISC Machnes (ARM) based Field Programmable Gate Array (FPGA) in prototyping smart card design with memory ciphering system. The smart card design is implemented in Xilinx's Zynq-7000 XC7020-1-CLG484 and Intel's Cyclone V System-on-a-Chp (SoC) 5 CSEMA 5 F 31 C6N devices. The objective of this study is to identify the optimum FPGA platform for the prototype. The comparative study between the two ARM-based FPGA implementations is explained in terms of logics utilization and time requirements. The memory ciphering system in the smart card is capable to complete in 40 nsec that is a single CPU clock cycle of the smart card. Results obtained showed that the implementation in the Intel Cyclone V SoC has the least utilized logics and the highest maximum frequency whch are 8.313 slices and 195 MHz, respectively. Since, the smart card prototyping in FPGA is the prerequisite for its Application Specific Integrated Circuit (ASIC) implementation, findngs from this study senre as a good reference for enhancing secure smart card performance especially for logic optimization in ASIC.

Original languageEnglish
Pages (from-to)2638-2646
Number of pages9
JournalJournal of Engineering and Applied Sciences
Volume13
Issue number9
DOIs
Publication statusPublished - 01 Jan 2018

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

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